100G Interlaken Intel® FPGA IP User Guide

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ID 683338
Date 9/20/2022
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Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. Getting Started With the 100G Interlaken IP Core 3. 100G Interlaken IP Core Parameter Settings 4. Functional Description 5. 100G Interlaken IP core Signals 6. 100G Interlaken IP Core Register Map 7. 100G Interlaken IP Core Test Features 8. Advanced Parameter Settings 9. Out-of-Band Flow Control in the 100G Interlaken IP core 10. 100G Interlaken IP core User Guide Archives 11. Document Revision History for 100G Interlaken User Guide A. Performance and Fmax Requirements for 100G Ethernet Traffic
1. About This IP Core x
1.1. Features 1.2. Device Family Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Device Speed Grade Support 1.6. Release Information
1.1. Features x
1.1.1. IP Core Supported Combinations of Number of Lanes and Data Rate 1.1.2. IP Core Theoretical Raw Aggregate Bandwidth
2. Getting Started With the 100G Interlaken IP Core x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the 100G Interlaken IP Core Parameters and Options 2.3. Files Generated for Arria V GZ and Stratix V Variations 2.4. Files Generated for Intel® Arria® 10 Variations 2.5. Simulating the 100G Interlaken IP Core 2.6. Integrating Your IP Core in Your Design 2.7. Compiling the Full Design and Programming the FPGA 2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignments 2.6.2. Transceiver Logical Channel Numbering 2.6.3. Adding the Reconfiguration Controller 2.6.4. Adding the External PLL
2.6.3. Adding the Reconfiguration Controller x
2.6.3.1. Generating the Reconfiguration Controller 2.6.3.2. Connecting the Reconfiguration Controller to the IP Core
3. 100G Interlaken IP Core Parameter Settings x
3.1. Number of Lanes 3.2. Meta Frame Length in Words 3.3. Data Rate 3.4. Transceiver Reference Clock Frequency 3.5. Include Advanced Error Reporting and Handling 3.6. Enable M20K ECC Support 3.7. Include Diagnostic Features 3.8. Enable Native PHY Debug Master Endpoint (NPDME) 3.9. Include In-Band Flow Control Block 3.10. Number of Calendar Pages 3.11. TX Scrambler Seed 3.12. Transfer Mode Selection 3.13. Data Format
4. Functional Description x
4.1. Interfaces Overview 4.2. High Level Block Diagram 4.3. Clocking and Reset Structure for IP Core 4.4. Interleaved and Packet Modes 4.5. Dual Segment Mode 4.6. M20K ECC Support 4.7. 100G Interlaken IP Core Transmit Path 4.8. 100G Interlaken IP Core Receive Path
4.1. Interfaces Overview x
4.1.1. Application Interface 4.1.2. Interlaken Interface 4.1.3. Out‑of‑Band Flow Control Interface 4.1.4. Management Interface 4.1.5. Transceiver Control Interfaces
4.1.5. Transceiver Control Interfaces x
4.1.5.1. Transceiver Reconfiguration Controller Interface 4.1.5.2. Intel® Arria® 10 External PLL Interface 4.1.5.3. Intel® Arria® 10 Transceiver Reconfiguration Interface
4.3. Clocking and Reset Structure for IP Core x
4.3.1. 100G Interlaken IP Core Clock Signals 4.3.2. IP Core Reset 4.3.3. IP Core Reset Sequence with the Reconfiguration Controller
4.7. 100G Interlaken IP Core Transmit Path x
4.7.1. 100G Interlaken IP Core Transmit User Data Interface Examples 4.7.2. 100G Interlaken IP Core In-Band Calendar Bits on Transmit Side 4.7.3. 100G Interlaken IP Core Transmit Path Blocks
4.7.1. 100G Interlaken IP Core Transmit User Data Interface Examples x
4.7.1.1. 100G Interlaken IP Core Interleaved Mode (Segmented Mode) Example 4.7.1.2. 100G Interlaken IP Core Packet Mode Operation Example 4.7.1.3. 100G Interlaken IP Core Back-Pressured Packet Transfer Example 4.7.1.4. 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Transmit Example
4.7.3. 100G Interlaken IP Core Transmit Path Blocks x
4.7.3.1. 100G Interlaken IP Core TX Transmit Buffer 4.7.3.2. 100G Interlaken IP Core TX MAC 4.7.3.3. 100G Interlaken IP Core TX PCS 4.7.3.4. 100G Interlaken IP Core TX PMA
4.8. 100G Interlaken IP Core Receive Path x
4.8.1. 100G Interlaken IP Core Receive User Data Interface Examples 4.8.2. 100G Interlaken IP Core RX Errored Packet Handling 4.8.3. In-Band Calendar Bits on the 100G Interlaken IP Core Receiver User Data Interface 4.8.4. 100G Interlaken IP Core Receive Path Blocks
4.8.1. 100G Interlaken IP Core Receive User Data Interface Examples x
4.8.1.1. 100G Interlaken IP Core Receiver Side Example 4.8.1.2. 100G Interlaken IP Core Dual Segment Interleaved Data Transfer Receive Example
4.8.2. 100G Interlaken IP Core RX Errored Packet Handling x
4.8.2.1. 100G Interlaken IP Core Receiver Side Example With Errors and In-Band Calendar Bits
4.8.4. 100G Interlaken IP Core Receive Path Blocks x
4.8.4.1. 100G Interlaken IP Core RX PMA 4.8.4.2. 100G Interlaken IP Core RX PCS 4.8.4.3. 100G Interlaken IP Core RX MAC 4.8.4.4. 100G Interlaken IP Core RX Regroup Block
5. 100G Interlaken IP core Signals x
5.1. 100G Interlaken IP Core Clock Interface Signals 5.2. 100G Interlaken IP Core Reset Interface Signals 5.3. 100G Interlaken IP Core User Data Transfer Interface Signals 5.4. 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals 5.5. 100G Interlaken IP Core Management Interface 5.6. Device Dependent Signals
5.6. Device Dependent Signals x
5.6.1. Transceiver Reconfiguration Controller Interface Signals 5.6.2. Intel® Arria® 10 External PLL Interface Signals 5.6.3. Intel® Arria® 10 Transceiver Reconfiguration Interface Signals
7. 100G Interlaken IP Core Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode 7.3. PRBS Generation and Validation 7.4. CRC32 Error Injection 7.5. CRC24 Error Injection
7.3. PRBS Generation and Validation x
7.3.1. Setting up PRBS Mode in Arria V and Stratix V Devices 7.3.2. Setting up PRBS Mode in Intel® Arria® 10 Devices
8. Advanced Parameter Settings x
8.1. Hidden Parameters 8.2. Modifying Hidden Parameter Values
8.1. Hidden Parameters x
8.1.1. Include Temp Sense 8.1.2. RXFIFO Address Width 8.1.3. SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping)
9. Out-of-Band Flow Control in the 100G Interlaken IP core x
9.1. Out-of-Band Flow Control Block Clocks 9.2. TX Out‑of‑Band Flow Control Signals 9.3. RX Out-of-Band Flow Control Signals
1. About This IP Core
2. Getting Started With the 100G Interlaken IP Core
3. 100G Interlaken IP Core Parameter Settings
4. Functional Description
5. 100G Interlaken IP core Signals
6. 100G Interlaken IP Core Register Map
7. 100G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 100G Interlaken IP core
10. 100G Interlaken IP core User Guide Archives
11. Document Revision History for 100G Interlaken User Guide
A. Performance and Fmax Requirements for 100G Ethernet Traffic

7.3.1. Setting up PRBS Mode in Arria V and Stratix V Devices

To enable the IP core to generate PRBS output, you must program the relevant hard PCS registers to enable the PRBS generator clock, to set the test_enable bit, and to select the PRBS polynomial. To enable the IP core to receive PRBS input, you must program the relevant hard PCS registers to enable the PRBS receiver clock, to set the test_enable bit, and to select the expected PRBS polynomial. If you perform your PRBS testing in loopback mode, you must enable the IP core to both generate and receive PRBS sequences.

The PRBS feature is available only if you turn on Include diagnostic features in the 100G Interlaken parameter editor.

This section describes the register values you must program. For instructions to program the registers that activate the PRBS test feature in your Arria V or Stratix V 100G Interlaken IP core, refer to the hard PCS register programming instructions in the Native PHY IP Core chapter for your target device family and in the Transceiver Reconfiguration Controller chapter of the Intel® Transceiver PHY IP Core User Guide.

Table 26.  Programming the Hard PCS Registers in Arria V and Stratix V Devices

To turn on the PRBS feature in the hard PCS, you must program the following hard PCS registers in the order shown, for each of the TX and RX sides. These registers are not accessible using the 100G Interlaken IP core Management interface. You must access these registers through the Transceiver Reconfiguration Controller that connects to the IP core.

Ensure you set these register bits using a read-modify-write register access sequence (per register), to avoid modifying the other register fields.

TX Register Offset Bits Meaning Action
1 0x141 [0] Invert TX channels Set this bit to the value of 0 to specify that the outgoing PRBS be inverted, or set this bit to the value of 1 to specify that the outgoing PRBS not be inverted. The default value of this register bit is 0. By default, the outgoing PRBS is inverted.
2 0x135 [10] Enable PRBS7 Set one of these bits to the value of 1, and the others to the value of 0, to select the TX polynomial.
[8] Enable PRBS23
[6] Enable PRBS9
[4] Enable PRBS31
[3] TX test enable Set this bit to the value of 1 to enable the PRBS pattern generator in the transmitter.
3 0x137 [2] Enable TX PRBS clock Set this bit to the value of 1 to enable the TX PRBS clock.
RX Register Offset Bits Meaning Action
1 0x16D [2] Invert RX channels Set this bit to the value of 0 to specify that the PCS should expect the incoming PRBS to be inverted, or set this bit to the value of 1 to specify that the PCS should not expect the incoming PRBS to be inverted. The default value of this bit is 0. In loopback mode, you should set this bit to match the setting in the PRBS transmitter.
2 0x15E [14] Enable PRBS7 Set one of these bits to the value of 1, and the others to the value of 0, to select the expected polynomial.
[13] Enable PRBS23
[12] Enable PRBS9
[11] Enable PRBS31
[10] RX test enable Set this bit to the value of 1 to enable the PRBS pattern verifier in the receiver.
3 0x164 [10] Enable RX PRBS clock Set this bit to the value of 1 to enable the RX PRBS clock.

After you activate an IP core that targets an Arria V or Stratix V device to generate PRBS output, it immediately begins transmitting PRBS output on the Interlaken link. After you enable the IP core to receive PRBS input, you can check the receive PRBS status in the 100G Interlaken IP core PRBS status registers (RX_PRBS_DONE, RX_PRBS_ERR, and RX_PRBS_COUNT).

After your testing is complete, you must reset these register bits to their default values to enable normal operation.

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