100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 9/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.5.2. Intel® Arria® 10 External PLL Interface

100G Interlaken IP core variations that target an Intel® Arria® 10 device require an external transceiver PLL to function correctly in hardware. 100G Interlaken IP core variations that target an Arria V or Stratix V device include the transceiver PLLs and do not require that you configure any additional PLLs.