Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 5/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. AXI-Stream Broadcaster Intel® FPGA IP x
10.1. About the AXI-Stream Broadcaster IP 10.2. AXI-Stream Broadcaster IP Parameters 10.3. AXI-Stream Broadcaster IP Interfaces
10.1. About the AXI-Stream Broadcaster IP x
10.1.1. AXI-Stream Broadcaster IP Features 10.1.2. AXI-Stream Broadcaster IP Performance and Resources
11. Bits per Color Sample Adapter Intel FPGA IP x
11.1. About the Bits per Color Sample Adapter IP 11.2. Bits per Color Sample Adapter IP Parameters 11.3. Bits per Color Sample Adapter IP Interfaces 11.4. Bits per Color Sample Adapter IP Registers 11.5. Bits per Color Sample Adapter Software API
11.1. About the Bits per Color Sample Adapter IP x
11.1.1. Bits per Color Sample Adapter IP Performance and Resources
12. Black Level Correction Intel® FPGA IP x
12.1. About the Black Level Correction IP 12.2. Black Level Correction IP Parameters 12.3. Black Level Correction IP Functional Description 12.4. Black Level Correction IP Registers 12.5. Black Level Correction IP Software API
12.1. About the Black Level Correction IP x
12.1.1. Black Level Correction IP Performance and Resources
12.3. Black Level Correction IP Functional Description x
12.3.1. Black Level Correction IP Interfaces
13. Black Level Statistics Intel® FPGA IP x
13.1. About the Black Level Statistics IP 13.2. Black Level Statistics IP Parameters 13.3. Black Level Statistics IP Interfaces 13.4. Black Level Statistics IP Registers 13.5. Black Level Statistics IP Software API
13.1. About the Black Level Statistics IP x
13.1.1. Black Level Statistics IP Performance and Resources
14. Chroma Key Intel® FPGA IP x
14.1. About the Chroma Key IP 14.2. Chroma Key IP Parameters 14.3. Chroma Key IP Interfaces 14.4. Chroma Key Replacement 14.5. Chroma Key IP Registers 14.6. Chroma Key IP Software API
14.1. About the Chroma Key IP x
14.1.1. Chroma Key IP Performance and Resources
15. Chroma Resampler Intel® FPGA IP x
15.1. About the Chroma Resampler IP 15.2. Chroma Resampler IP Parameters 15.3. Chroma Resampler IP Functional Description 15.4. Chroma Resampler IP Registers 15.5. Chroma Resampler IP Software API
15.1. About the Chroma Resampler IP x
15.1.1. Chroma Resampler Performance and Resources
15.3. Chroma Resampler IP Functional Description x
15.3.1. Chroma Resampler IP Interfaces
16. Clipper Intel® FPGA IP x
16.1. About the Clipper IP 16.2. Clipper IP Parameters 16.3. Clipper IP Interfaces 16.4. Clipper IP Registers 16.5. Clipper IP Software API
16.1. About the Clipper IP x
16.1.1. Clipper IP Performance and Resources
17. Clocked Video Input Intel® FPGA IP x
17.1. About the Clocked Video Input IP 17.2. Initializing the Clocked Video Input IP 17.3. Clocked Video Input IP Parameters 17.4. Clocked Video Input IP Interfaces 17.5. Clocked Video Input IP Registers 17.6. Clocked Video Input IP Software API
17.1. About the Clocked Video Input IP x
17.1.1. Clocked Video Input IP Features 17.1.2. Clocked Video Input IP Performance and Resources
18. Clocked Video to Full-Raster Converter Intel® FPGA IP x
18.1. About the Clocked Video to Full-Raster Converter IP 18.2. Clocked Video to Full-Raster Converter Parameters 18.3. Clocked Video to Full-Raster Converter Block Description 18.4. Clocked Video Converter to Full-Raster IP Registers
18.1. About the Clocked Video to Full-Raster Converter IP x
18.1.1. Clocked Video to Full-Raster Converter Features 18.1.2. Clocked Video to Full-Raster Converter Performance and Resources
18.3. Clocked Video to Full-Raster Converter Block Description x
18.3.1. Clocked Video to Full-Raster Converter Interfaces
19. Clocked Video Output Intel® FPGA IP x
19.1. About the Clocked Video Output IP 19.2. Clocked Video Output IP Parameters 19.3. Clocked Video Output IP Functional Description 19.4. Clocked Video Output IP Interfaces 19.5. Clocked Video Output IP Registers 19.6. Clocked Video Output IP Software API
19.1. About the Clocked Video Output IP x
19.1.1. Clocked Video Output IP Performance and Resources 19.1.2. Clocked Video Output IP Features
20. Color Plane Manager Intel® FPGA IP x
20.1. About the Color Plane Manager IP 20.2. Color Plane Manager IP Parameters 20.3. Color Plane Manager IP Functional Description 20.4. Color Plane Manager IP Registers 20.5. Color Plane Manager Software API
20.1. About the Color Plane Manager IP x
20.1.1. Color Plane Manager IP Performance and Resources
20.3. Color Plane Manager IP Functional Description x
20.3.1. Color Plane Manager IP Interfaces
21. Color Space Converter Intel® FPGA IP x
21.1. About the Color Space Converter IP 21.2. Color Space Converter IP Parameters 21.3. Color Space Converter IP Functional Description 21.4. Color Space Converter IP Registers 21.5. Color Space Converter IP Software API
21.1. About the Color Space Converter IP x
21.1.1. Color Space Converter IP Features 21.1.2. Color Space Converter IP Performance and Resources
21.3. Color Space Converter IP Functional Description x
21.3.1. Color Space Converter IP Interfaces
22. Defective Pixel Correction Intel® FPGA IP x
22.1. About the Defective Pixel Correction IP 22.2. Defective Pixel Correction IP Parameters 22.3. Defective Pixel Correction IP Functional Description 22.4. Defective Pixel Correction IP Registers 22.5. Defective Pixel Correction IP Software API
22.1. About the Defective Pixel Correction IP x
22.1.1. Defective Pixel Correction IP Performance and Resources
22.3. Defective Pixel Correction IP Functional Description x
22.3.1. Defective Pixel Correction IP Interfaces
23. Deinterlacer Intel® FPGA IP x
23.1. About the Deinterlacer IP 23.2. Deinterlacer Parameters 23.3. Deinterlacer Interfaces 23.4. Deinterlacer IP Registers 23.5. Deinterlacer IP Software API
23.1. About the Deinterlacer IP x
23.1.1. Deinterlacer Performance and Resources
24. Demosaic Intel® FPGA IP x
24.1. About the Demosaic IP 24.2. Demosaic IP Parameters 24.3. Demosaic IP Functional Description 24.4. Demosaic IP Registers 24.5. Demosaic IP Software API
24.1. About the Demosaic IP x
24.1.1. Demosaic IP Performance and Resources
24.3. Demosaic IP Functional Description x
24.3.1. Demosaic IP Interfaces
25. FIR Filter Intel® FPGA IP x
25.1. About the FIR Filter 25.2. FIR Filter Parameters 25.3. FIR Filter IP Operation 25.4. FIR Filter Interfaces 25.5. FIR Filter Registers 25.6. FIR Filter IP Software API
25.1. About the FIR Filter x
25.1.1. FIR Filter IP Performance and Resources
25.3. FIR Filter IP Operation x
25.3.1. FIR Filter Processing 25.3.2. FIR Filter Precision 25.3.3. FIR Coefficient Specification 25.3.4. FIR Filter Symmetry 25.3.5. Result to Output Data Type Conversion
25.3.4. FIR Filter Symmetry x
25.3.4.1. No Symmetry 25.3.4.2. Horizontal Symmetry 25.3.4.3. Vertical Symmetry 25.3.4.4. Horizontal and Vertical Symmetry 25.3.4.5. Diagonal Symmetry
26. Frame Cleaner Intel® FPGA IP x
26.1. About the Frame Cleaner IP 26.2. Frame Cleaner IP Parameters 26.3. Frame Cleaner IP Functional Description 26.4. Frame Cleaner IP Interfaces 26.5. Frame Cleaner IP Registers 26.6. Frame Cleaner IP Software API
26.1. About the Frame Cleaner IP x
26.1.1. Frame Cleaner IP Performance and Resources
27. Full-Raster to Clocked Video Converter Intel® FPGA IP x
27.1. About the Full-Raster to Clocked Video Converter 27.2. Full Raster to Clocked Video Converter Parameters 27.3. Full-Raster to Clocked Video Converter Block Description 27.4. Full-Raster to Clocked Video Converter Registers
27.1. About the Full-Raster to Clocked Video Converter x
27.1.1. Full-Raster to Clocked Video Converter Features 27.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
27.3. Full-Raster to Clocked Video Converter Block Description x
27.3.1. Full Raster to Clocked Video Converter Interfaces
28. Full-Raster to Streaming Converter Intel® FPGA IP x
28.1. About the Full-Raster to Streaming Converter IP 28.2. Full-Raster to Streaming Converter Parameters 28.3. Full-Raster to Streaming Converter Block Description
28.1. About the Full-Raster to Streaming Converter IP x
28.1.1. Full-Raster to Streaming Converter Features 28.1.2. Full-Raster to Streaming Converter Performance and Resources
28.3. Full-Raster to Streaming Converter Block Description x
28.3.1. Full-Raster to Streaming Converter Interfaces
29. Genlock Controller Intel® FPGA IP x
29.1. About the Genlock Controller IP 29.2. Genlock Controller IP Parameters 29.3. Genlock Controller IP Functional Description 29.4. Using Genlock Controller IP Software 29.5. Genlock Controller IP Registers 29.6. Genlock Controller IP Software API
29.1. About the Genlock Controller IP x
29.1.1. Genlock Controller IP Performance and Resources
29.3. Genlock Controller IP Functional Description x
29.3.1. Genlock Controller IP Interfaces
29.4. Using Genlock Controller IP Software x
29.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 29.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 29.4.3. Setting the VCXO hold over 29.4.4. Restarting the Genlock Controller IP 29.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 29.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 29.4.7. Disturbing a Reference Clock (a cable pull)
30. Generic Crosspoint Intel® FPGA IP x
30.1. About the Generic Crosspoint IP 30.2. Generic Crosspoint IP Parameters 30.3. Generic Crosspoint IP Interfaces 30.4. Generic Crosspoint IP Registers 30.5. Generic Crosspoint IP Software API
30.1. About the Generic Crosspoint IP x
30.1.1. Generic Crosspoint IP Features 30.1.2. Generic Crosspoint Performance and Resources
31. Genlock Signal Router Intel® FPGA IP x
31.1. About the Genlock Signal Router IP 31.2. Genlock Signal Router IP Parameters 31.3. Genlock Signal Router IP Interfaces 31.4. Genlock Signal Router IP Registers 31.5. Genlock Signal Router IP Software API
31.1. About the Genlock Signal Router IP x
31.1.1. Genlock Signal Router IP Features 31.1.2. Genlock Signal Router IP Performance and Resources
32. Guard Bands Intel® FPGA IP x
32.1. About the Guard Bands IP 32.2. Guard Bands IP Parameters 32.3. Guard Bands IP Interfaces 32.4. Guard Bands IP Registers 32.5. Guard Bands IP Software API
32.1. About the Guard Bands IP x
32.1.1. Guard Bands IP Performance and Resources
33. Histogram Statistics Intel® FPGA IP x
33.1. About the Histogram Statistics IP 33.2. Histogram Statistics IP Parameters 33.3. Histogram Statistics IP Interfaces 33.4. Histogram Statistics IP Registers 33.5. Histogram Statistics IP Software API
33.1. About the Histogram Statistics IP x
33.1.1. Histogram Statistics IP Performance and Resources
34. Interlacer Intel® FPGA IP x
34.1. About the Interlacer IP 34.2. Interlacer IP Parameters 34.3. Interlacer IP Functional Description 34.4. Interlacer IP Registers 34.5. Interlacer IP Software API
34.1. About the Interlacer IP x
34.1.1. Interlacer IP Performance and Resources
34.3. Interlacer IP Functional Description x
34.3.1. Interlacer IP Interfaces
35. Mixer Intel® FPGA IP x
35.1. About the Mixer IP 35.2. Mixer IP Parameters 35.3. Mixer IP Functional Description 35.4. Mixer IP Registers 35.5. Mixer IP Software API
35.1. About the Mixer IP x
35.1.1. Mixer IP Performance and Resources
35.3. Mixer IP Functional Description x
35.3.1. Mixer IP Interfaces
36. Pixels in Parallel Converter Intel® FPGA IP x
36.1. About the Pixels in Parallel Converter IP 36.2. Pixels in Parallel Converter IP Parameters 36.3. Pixels in Parallel Converter Interfaces 36.4. Pixels in Parallel Converter Registers 36.5. Pixels in Parallel Converter IP Software API
36.1. About the Pixels in Parallel Converter IP x
36.1.1. Pixels in Parallel Converter IP Performance and Resources
37. Scaler Intel® FPGA IP x
37.1. About the Scaler 37.2. Scaler IP Parameters 37.3. Scaler IP Functional Description 37.4. Scaler IP Registers 37.5. Scaler IP Software API
37.1. About the Scaler x
37.1.1. Scaler IP Performance and Resources
37.2. Scaler IP Parameters x
37.2.1. Scaler Maximum Resolution
37.3. Scaler IP Functional Description x
37.3.1. Coefficient Selection 37.3.2. Coefficient Quantization 37.3.3. Filter Behavior at Edge Boundaries 37.3.4. Partial Frame Scaling 37.3.5. 422 and 420 Chroma Sampled Data Scaling 37.3.6. Scaler IP Interfaces
37.3.1. Coefficient Selection x
37.3.1.1. Updating Scaler IP Runtime Coefficients
38. Stream Cleaner Intel® FPGA IP x
38.1. About the Stream Cleaner IP 38.2. Stream Cleaner IP Parameters 38.3. Stream Cleaner IP Functional Description
38.1. About the Stream Cleaner IP x
38.1.1. Stream Cleaner IP Performance and Resources
38.3. Stream Cleaner IP Functional Description x
38.3.1. Stream Cleaner IP Interfaces
39. Switch Intel® FPGA IP x
39.1. About the Switch IP 39.2. Switch IP Parameters 39.3. Switch IP Functional Description 39.4. Switch IP Registers 39.5. Switch IP Software API
39.1. About the Switch IP x
39.1.1. Switch IP Performance and Resources
39.3. Switch IP Functional Description x
39.3.1. Switch IP Latency 39.3.2. Switch IP Interfaces
40. Tone Mapping Operator Intel® FPGA IP x
40.1. About the Tone Mapping Operator IP 40.2. TMO IP Parameters 40.3. TMO IP Block Description 40.4. TMO IP Registers 40.5. TMO IP Software API
40.1. About the Tone Mapping Operator IP x
40.1.1. TMO IP Features 40.1.2. TMO IP Performance and Resource Utilization
40.3. TMO IP Block Description x
40.3.1. TMO IP Interfaces 40.3.2. TMO IP Latency
41. Test Pattern Generator Intel® FPGA IP x
41.1. About the Test Pattern Generator IP 41.2. Test Pattern Generator IP Parameters 41.3. Test Pattern Generator IP Functional Description 41.4. Test Pattern Generator IP Registers 41.5. Test Pattern Generator IP Software API
41.1. About the Test Pattern Generator IP x
41.1.1. Test Pattern Generator IP Performance and Resources
41.3. Test Pattern Generator IP Functional Description x
41.3.1. Test Pattern Generator IP Interfaces
42. Unsharp Mask Intel® FPGA IP x
42.1. About the Unsharp Mask IP 42.2. Unsharp Mask IP Parameters 42.3. Unsharp Mask IP Functional Description 42.4. Unsharp Mask IP Registers 42.5. Unsharp Mask IP Software API
42.1. About the Unsharp Mask IP x
42.1.1. Unsharp Mask IP Performance and Resources
42.3. Unsharp Mask IP Functional Description x
42.3.1. Unsharp Mask IP Interfaces
43. Video and Vision Monitor Intel FPGA IP x
43.1. About the Video and Vision Monitor IP 43.2. Video and Vision Monitor IP Parameters 43.3. Video and Vision Monitor IP Functional Description 43.4. Video and Vision Monitor IP Registers 43.5. Video and Vision Monitor Software API
43.1. About the Video and Vision Monitor IP x
43.1.1. Video and Vision Monitor IP Performance and Resources
43.3. Video and Vision Monitor IP Functional Description x
43.3.1. Video and Vision Monitor IP Interfaces
44. Video Frame Buffer Intel® FPGA IP x
44.1. About the Video Frame Buffer IP 44.2. Video Frame Buffer IP Parameters 44.3. Video Frame Buffer IP Functional Description 44.4. Video Frame Buffer IP Registers 44.5. Video Frame Buffer IP Software API
44.1. About the Video Frame Buffer IP x
44.1.1. Video Frame Buffer Performance and Resources
44.3. Video Frame Buffer IP Functional Description x
44.3.1. Video Frame Buffer IP Interfaces
45. Video Frame Reader Intel FPGA IP x
45.1. About the Video Frame Reader IP 45.2. Video Frame Reader IP Parameters 45.3. Video Frame Reader IP Functional Description 45.4. Video Frame Reader IP Registers 45.5. Video Frame Reader IP Software API
45.1. About the Video Frame Reader IP x
45.1.1. Video Frame Reader IP Performance and Resources
45.3. Video Frame Reader IP Functional Description x
45.3.1. Video Frame Reader IP Interfaces
46. Video Frame Writer Intel FPGA IP x
46.1. About the Video Buffer Writer IP 46.2. Video Frame Writer IP Parameters 46.3. Video Frame Writer IP Functional Description 46.4. Video Frame Writer IP Registers 46.5. Video Frame Writer IP Software API
46.1. About the Video Buffer Writer IP x
46.1.1. Video Frame Writer IP Performance and Resources
46.3. Video Frame Writer IP Functional Description x
46.3.1. Video Frame Writer IP Interfaces
47. Video Streaming FIFO Intel® FPGA IP x
47.1. About the Video Streaming FIFO IP 47.2. Video Streaming FIFO IP Parameters 47.3. Video Streaming FIFO IP Interfaces
47.1. About the Video Streaming FIFO IP x
47.1.1. Video Streaming FIFO IP Performance and Resources
48. Video Timing Generator Intel® FPGA IP x
48.1. About the Video Timing Generator IP 48.2. Video Timing Generator IP Parameters 48.3. Video Timing Generator IP Functional Description 48.4. Video Timing Generator IP Interfaces 48.5. Video Timing Generator IP Registers 48.6. Video Timing Generator IP Software API
48.1. About the Video Timing Generator IP x
48.1.1. Video Timing Generator IP Features 48.1.2. Video Timing Generator IP Performance and Resources
49. Vignette Correction Intel® FPGA IP x
49.1. About the Vignette Correction IP 49.2. Vignette Correction IP Parameters 49.3. Vignette Correction IP Interfaces 49.4. Vignette Correction IP Registers 49.5. Vignette Correction IP Software API
49.1. About the Vignette Correction IP x
49.1.1. Vignette Correction IP Performance and Resources
50. Warp Intel® FPGA IP x
50.1. About the Warp IP 50.2. Warp IP Parameters 50.3. Warp IP Block Description 50.4. Warp IP Registers 50.5. Warp IP Software API
50.1. About the Warp IP x
50.1.1. Warp IP Features 50.1.2. Warp IP Performance and Resource Utilization
50.3. Warp IP Block Description x
50.3.1. Block Cache Tool 50.3.2. Warp IP Interfaces 50.3.3. Warp IP Latency 50.3.4. External Memory for Warp IP
50.5. Warp IP Software API x
50.5.1. Using Warp IP Software 50.5.2. Warp IP Software Code Examples
51. White Balance Correction Intel® FPGA IP x
51.1. About the White Balance Correction IP 51.2. White Balance Correction IP Parameters 51.3. White Balance Correction IP Functional Description 51.4. White Balance Correction IP Registers 51.5. White Balance Correction IP Software API
51.1. About the White Balance Correction IP x
51.1.1. White Balance Correction IP Performance and Resources
51.3. White Balance Correction IP Functional Description x
51.3.1. White Balance Correction IP Interfaces
52. White Balance Statistics Intel® FPGA IP x
52.1. About the White Balance Statistics IP 52.2. White Balance Statistics IP Parameters 52.3. White Balance Statistics IP Interfaces 52.4. White Balance Statistics IP Registers 52.5. White Balance Statistics IP Software API
52.1. About the White Balance Statistics IP x
52.1.1. White Balance Statistics IP Performance and Resources
53. Design Security x
53.1. Memory Subsystems 53.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. AXI-Stream Broadcaster Intel® FPGA IP
11. Bits per Color Sample Adapter Intel FPGA IP
12. Black Level Correction Intel® FPGA IP
13. Black Level Statistics Intel® FPGA IP
14. Chroma Key Intel® FPGA IP
15. Chroma Resampler Intel® FPGA IP
16. Clipper Intel® FPGA IP
17. Clocked Video Input Intel® FPGA IP
18. Clocked Video to Full-Raster Converter Intel® FPGA IP
19. Clocked Video Output Intel® FPGA IP
20. Color Plane Manager Intel® FPGA IP
21. Color Space Converter Intel® FPGA IP
22. Defective Pixel Correction Intel® FPGA IP
23. Deinterlacer Intel® FPGA IP
24. Demosaic Intel® FPGA IP
25. FIR Filter Intel® FPGA IP
26. Frame Cleaner Intel® FPGA IP
27. Full-Raster to Clocked Video Converter Intel® FPGA IP
28. Full-Raster to Streaming Converter Intel® FPGA IP
29. Genlock Controller Intel® FPGA IP
30. Generic Crosspoint Intel® FPGA IP
31. Genlock Signal Router Intel® FPGA IP
32. Guard Bands Intel® FPGA IP
33. Histogram Statistics Intel® FPGA IP
34. Interlacer Intel® FPGA IP
35. Mixer Intel® FPGA IP
36. Pixels in Parallel Converter Intel® FPGA IP
37. Scaler Intel® FPGA IP
38. Stream Cleaner Intel® FPGA IP
39. Switch Intel® FPGA IP
40. Tone Mapping Operator Intel® FPGA IP
41. Test Pattern Generator Intel® FPGA IP
42. Unsharp Mask Intel® FPGA IP
43. Video and Vision Monitor Intel FPGA IP
44. Video Frame Buffer Intel® FPGA IP
45. Video Frame Reader Intel FPGA IP
46. Video Frame Writer Intel FPGA IP
47. Video Streaming FIFO Intel® FPGA IP
48. Video Timing Generator Intel® FPGA IP
49. Vignette Correction Intel® FPGA IP
50. Warp Intel® FPGA IP
51. White Balance Correction Intel® FPGA IP
52. White Balance Statistics Intel® FPGA IP
53. Design Security
54. Document Revision History for Video and Vision Processing Suite User Guide

45.4. Video Frame Reader IP Registers

Each register is either read-only (RO) or read-write (RW).

Main register set

Table 833.  Video Frame Reader IP Registers

In the software API, the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_VIDEO FRAME READER as appropriate and with an optional REG suffix

Address Register Access Description
Parameterization registers
0x0000 VID_PID RO Read this register for the Video Frame Reader product ID. This register always returns 0x6AF7_024A.
0x0004 VERSION RO Read this register for the IP version information.
0x0008 LITE_MODE RO

Read this register to determine if Lite mode is on or off.

This register returns 0 when Lite mode is off and 1 when on.

0x000C DEBUG_ENABLED RO Read this register to determine if Debug features is on.
0x0010 MAX_BUFFER_SETS RO Read this register to determine the maximum supported number of buffer sets.
0x0014 MAX_HEIGHT RO Read this register to determine the maximum supported frame height.
0x0018 MAX_WIDTH RO Read this register to determine the maximum supported frame width.
0x001C BITS_PER_SYMBOL RO Read this register for the number of bits per symbol configured.
0x0020 NUMBER_OF_COLOR_PLANES RO Read this register for the number of color planes.
0x0024 PIXELS_IN_PARALLEL RO Read this register for the number of pixels in parallel.
0x0028 PACKING RO Read this register for the pixel packing scheme.

0x002C to 0x00FF

Reserved
Interrupt registers
0x0100 IRQ_CONTROL RW

Set bit 0 to 1 to enable interrupts on completion of field reads

0x0104 IRQ_STATUS RW

Read the status register to see if the interrupt fired. If it did, the IP sets bit 0. To clear the interrupt, write a 1 to bit 0.

0x0107 to 0x013F

Reserved.
Control and Debug Registers
0x0140 STATUS RO

Bit 0: status bit.

1 = Video Frame Reader is outputting a video field, 0 otherwise.

Bit 1: Pending RTC control bit. Goes high when a write occurs to one of the control registers. Goes low at the end of the current frame if the IP makes a write to the COMMIT register.

0x0144 LAST_BUFFER_READ RO Returns the base address of the frame that the IP last produced. This register returns 0xFFFF_FFFF if the IP reads no buffers since reset.
0x0147-0x018F Reserved
0x0190 COMMIT RW Commit register.
0x0194 NUM_BUFFER_SETS RW

Instructs the frame reader how many buffer sets to configure.

0x0198 BUFFER_MODE RW Buffer mode.
0x019C STARTING_BUFFER_SET RW Starting buffer set.
0x01A0 RUN RW

Set the required operating mode:

0 = Frame reader is not running (stopped)

1 = Frame reader is free-running mode.

2 = Frame reader is in frame sync mode. In this mode the reader starts the output on receiving a frame sync and stops when the field is output.

3 = Frame reader is in single-shot mode. In this mode, BUFFER_N_NUM_BUFFERS decides how many buffers are read from. After the IP reads all the buffers from the current set (or all sets if BUFFER_MODE is set to 1), output stops. To perform another single-shot read, write to the COMMIT register.

0x01A4 FSYNC_PULSE_MODE RW Frame sync pulse mode.

Buffer set register banks

In addition to the main register set, the IP has one bank of registers per configured buffer set. Program the buffer set register banks with the relevant details for each set. The IP calculates the base address in hex for each register bank according to the buffer set number, which is an integer from 0 to MAX_BUFFER_SETS:

For example, buffer set 0 registers are at 0x01B0 + 0 = 0x01B0.

For example, buffer set 1 registers are at 0x01B0 + 1x 0x40 = 0x01F0.

For example, buffer set 3 registers are at 0x01B0 + 3x 0x40 = 0x0270.

Table 834.  Buffer set register banks
Address Register Access Description
0x01B0 + N*0x40 BUFFER_N_BASE RW Buffer base address
0x01B4 + N*0x40 BUFFER_N_NUM_BUFFERS RW Number of buffers in this buffer set. Often set to 1 for common double-buffering applications.
0x01B8 + N*0x40 BUFFER_N_INTER_BUFFER_OFFSET RW

Interbuffer address increment.

If BUFFER_N_NUM_BUFFERS is set to 1, this register is unused.

0x01BC + N*0x40 BUFFER_N_INTER_LINE_OFFSET RW Interline address increment.
0x01C0 + N*0x40 BUFFER_N_WIDTH RW For outgoing image information packets if Lite mode is off.
0x01C4 + N*0x40 BUFFER_N_HEIGHT RW For outgoing image information packets if Lite mode is off and to determine how many lines to read from the BASE address.
0X01C8 + N*0x40 BUFFER_N_INTERLACE RW For outgoing image information packets if Lite mode is off and to set TUSER[1] unless BUFFER_0_PACKED_INTERLACE is non-zero.
0x01CC + N*0x40 BUFFER_N_COLORSPACE RW For outgoing image information packets if Lite mode is off.
0x01D0 + N*0x40 BUFFER_N_SUBSAMPLING RW For outgoing image information packets if Lite mode is off.
0x01D4 + N*0x40 BUFFER_N_COSITING RW For outgoing image information packets if Lite mode is off.
0x01D8 + N*0x40 BUFFER_N_BPS RW For outgoing image information packets if Lite mode is off.
0x01DC + N*0x40 BUFFER_N_FIELD_COUNT RW For outgoing image information (low 7 bits) and EOF packets for field count quantities if Lite mode is off.

Register Bit Descriptions

Table 835.  VID_PID
Name Bits Description
Frame reader version ID and product ID 31:0

This register always returns 0x6AF7_024A

  • 15:0 is the product ID and always returns 0x024A
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 836.  VERSION
Name Bits Description
Register map version 7:0 Register map version.
IP patch revision 15:8 -
IP update revision 23:16 Updated when the IP version changes.
IP major revision 31:24 Updated when the IP version changes.
Table 837.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on lite mode.
Unused 31:1 Unused.
Table 838.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on Debug features.
Unused 31:1 Unused.
Table 839.  MAX_BUFFER_SETS
Name Bits Description
Max buffer sets 5:0 This register returns the maximum supported number of buffer sets.
Table 840.  MAX_WIDTH
Name Bits Description
Max width 31:0 This register returns the maximum supported frame width.
Table 841.  MAX_HEIGHT
Name Bits Description
Max height 31:0 This register returns the maximum supported frame height.
Table 842.  BITS_PER_SYMBOL
Name Bits Description
Bits per symbol 31:0 This register returns the number of bits per symbol that the Intel streaming video output is configured for.
Table 843.  NUMBER_OF_COLOR_PLANES
Name Bits Description
Number of color planes 31:0 This register returns the number of color planes that the Intel streaming video output is configured for.
Table 844.  PIXELS_IN_PARALLEL
Name Bits Description
Number of pixels in parallel 31:0 This register returns the number of pixels in parallel that the Intel streaming video output is configured for.
Table 845.  PACKING
Name Bits Description
Packing 31:0

This register returns the packing scheme that the IP uses:

  • 0 = Perfect packing
  • 1 = Color packing
  • 2 = Pixel packing
Table 846.   IRQ_CONTROL
Name Bit Description
Field_read_irq 0

Set the field_read_irq bit of the IRQ_CONTROL register to enable interrupts on completing field reads.

Clear to disable interrupts on completion of field reads

Table 847.   IRQ_STATUS
Name Bit Description
Field_read_irq 0

The field_read_irq bit of the IRQ_CONTROL register is set if the interrupt has fired.

Write to the field_read_irq bit of the IRQ_CONTROL register to clear down any interrupts.

Table 848.  STATUS
Name Bit Description
Status 0 Read this register to determine the status of the frame reader. The status bit is set if the reader is currently outputting a frame and returns to 0 in between frames.
Pending run-time control 1 Read this register to determine whether any pending register writes exist that have yet to be committed. This bit goes high when a write occurs to one of the control registers and returns low at the end of the current frame when a write has been made to the COMMIT register. If the frame reader is idle, this bit goes low directly after a write to the COMMIT register.
Table 849.  LAST_BUFFER_READ
Name Bit Description
Last buffer read 31:0 Read this register to determine the base address of the most recent output buffer. After a reset, if no buffers appear, this register returns 0xFFFF_FFFF.
Table 850.  COMMIT
Name Bit Description
Commit 0 Write to this register to commit the current register settings. The IP starts operating according to the new settings when it produces the current frame.
Table 851.  NUM_BUFFER_SETS
Name Bits Description
Number of buffer sets 31:0

Set this register to the number of buffer sets that you want.

The IP reads from buffers within each buffer set in turn.

For a typical memory-mapped graphics double buffer application, you might set up two buffer sets, each containing just one buffer. Software tick-tocks between the buffers under API control using the STARTING_BUFFER_SET register.

Legal values are between 1 and the maximum number of buffer sets you set in the GUI. To save area, the maximum number of buffer sets you set in the GUI restricts the number of buffer sets that the IP can use, as each set requires its own bank of registers. Setting this register to a value greater than MAX_BUFFER_STRUCTURES means the IP configures only one buffer set.

This register is the number of buffer sets that the IP actively uses. Do not confuse it with the maximum number of buffer sets you set in the GUI.

Table 852.  BUFFER_MODE
Name Bit Description
Buffer mode 1

Set this register according to the behavior you want:

0 = Read buffers in STARTING_BUFFER_SET only.

1 = Reads all buffer sets in turn, starting at STARTING_BUFFER_SET.

Table 853.  STARTING_BUFFER_SET
Name Bits Description
Starting buffer set 31:0 Set this register to a value from 0 to NUM_BUFFER_SETS to identify the starting buffer set.

Set this register to indicate the buffer set that you want to read from. For example, to read the first buffer from the buffer set at BUFFER_3_BASE, set this register to 3.

When starting reading from a new set, the first buffer in the set is output first.

Read LAST_BUFFER_READ(0x0144)to determine which buffer from the set was last read and output.

Reading starts from a new buffer set according to this register from STARTING_BUFFER_SET with the COMMIT register.

Table 854.  RUN
Name Bit Description
Run LSB 0

Set this bit to start the IP.

Clear this bit and clear the MSB to halt the IP.
Run MSB 1

If the LSB is set and this bit is clear, the IP operates in continuous (free-running) mode.

If the LSB is set, set this bit to configure the IP in single-shot mode. In this mode, BUFFER_N_NUM_BUFFERS dictates how many buffers are read from the current set, N. After the IP reads all the buffers from the current set (if BUFFER_MODE is set to 1), output stops. To perform another single-shot read, write to the COMMIT register.

If the LSB is clear, clear this bit to stop the IP at the end of the current frame read.

If the LSB is clear, set this bit to configure frame sync mode. In this mode, the reader produces one frame per frame sync.

Table 855.  FSYNC_PULSE_MODE
Name Bit Description
FSYNC pulse mode 0

If set, when operating in frame sync mode, the frame reading is triggered by a rising edge on the frame sync conduit.

If clear, when operating in frame sync mode, the frame reading is triggered by a rising or falling edge on the frame sync conduit (toggle mode).

Table 856.  BUFFER_N_BASE
Name Bits Description
buffer set N base address 31:0 Set this to the base address of buffer set N.
Table 857.  BUFFER_N_NUM_BUFFERS
Name Bits Description
buffer set N number of buffers 31:0 Set this to the number of buffers in set N.
Table 858.  BUFFER_N_INTER_BUFFER_OFFSET
Name Bits Description
buffer set N inter-buffer offset 31:0

Set this to the inter-buffer address increment for set N.

Usually this is equal or greater than bytes per line * BUFFER_N_HEIGHT.

Table 859.  BUFFER_N_INTER_LINE_OFFSET
Name Bits Description
buffer set N inter-line offset 31:0

Set this to the interline address increment for set N.

Usually bytes per pixel * BUFFER_N_WIDTH.

Table 860.  BUFFER_N_WIDTH
Name Bits Description
buffer set N buffer width 16:0 Set this to the width in pixels of the buffers in set N. If lite mode is off, the IP uses it also for outgoing image information packets.
Table 861.  BUFFER_N_HEIGHT
Name Bits Description
buffer set N buffer height 16:0 Set this to the height in pixels of the buffers in set N. If lite mode is off, the IP uses it also for outgoing image information packets.
Table 862.  BUFFER_N_INTERLACE
Name Bits Description
buffer set N interlace nibble 3:0 For outgoing image information packets if Lite mode is off and to set TUSER[1] if Lite mode is on.
Table 863.  BUFFER_N_COLORSPACE
Name Bits Description
buffer set N buffer colorspace 6:0 If Lite mode is off, for outgoing image information packets. Unused if Lite mode is on.
Table 864.  BUFFER_N_SUBSAMPLING
Name Bits Description
buffer set N buffer subsampling 1:0 If Lite mode is off, for outgoing image information packets. Unused if Lite mode is on.
Table 865.  BUFFER_N_COSITING
Name Bits Description
buffer set N buffer cositing 1:0 If Lite mode is off, for outgoing image information packets. Unused if Lite mode is on.
Table 866.  BUFFER_N_BPS
Name Bits Description
buffer set N buffer BPS 4:0 If Lite mode is off, for outgoing image information packets. Unused if Lite mode is on.
Table 867.  BUFFER_N_FIELD_COUNT
Name Bits Description
buffer set N starting field count 15:0 If Lite mode is off, the starting field count for outgoing image information and EOF packets. The image information and EOF field counts increment for each frame output and reset to this value after a write to COMMIT. Unused if Lite mode is on.
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