Visible to Intel only — GUID: hpl1708080480988
Ixiasoft
Visible to Intel only — GUID: hpl1708080480988
Ixiasoft
20.4. Color Plane Manager IP Registers
Address | Register | Access | Description | |
---|---|---|---|---|
Parameterization registers | ||||
0x0000 | VID_PID | RO | - | Read this register for the color plane manager product ID. This register always returns 0x6AF7_023B. |
0x0004 | VERSION | RO | - | Read this register for the IP version information |
0x0008 | LITE_MODE | RO | - | This register returns 1 if you select Lite Mode for the IP. |
0x000C | DEBUG_ENABLED | RO | - | Read this register to determine if debug features are on. |
0x0010 | BITS_PER_SYMBOL | RO | - | Read this register for bits per symbol configuration information. |
0x0014 | PIXELS_IN_PARALLEL | RO | - | Read this register for pixels in parallel configuration information. |
0x0018 | NUMBER_OF_INPUT_COLOR_PLANES | RO | - | Read this register for input color plane configuration information. |
0x001C | NUMBER_OF_OUTPUT_COLOR_PLANES | RO | - | Read this register for output color plane configuration information. |
0x0020 | MAPPING_FOR_OUTPUT_COLOR_PLANE0 | RO | - | Read this register for color plane 0 mapping information. |
0x0024 | MAPPING_FOR_OUTPUT_COLOR_PLANE1 | RO | - | Read this register for color plane 1 mapping information. |
0x0028 | MAPPING_FOR_OUTPUT_COLOR_PLANE2 | RO | - | Read this register for color plane 2 mapping information. |
0x002C | MAPPING_FOR_OUTPUT_COLOR_PLANE3 | RO | - | Read this register for color plane 3 mapping information. |
0x0030 to 0x011F |
Reserved | |||
Control and Debug registers |
||||
0x0120 | IMG_INFO_WIDTH | RW | RO | For lite designs, the expected width of the incoming video fields. For full designs, the received width in the IP derives from the image information packets. |
0x0124 | IMG_INFO_HEIGHT | RW | RO | For lite designs, the expected height of the incoming video fields. For full designs, the received height in the IP derives from the image information packets. |
0x0128 | IMG_INFO_INTERLACE | RW | RO | For lite designs, the expected interlace information of the incoming video fields. For full designs, the received interlace information in image information packets. |
0x012C | RESERVED | RW | RO | Unused. |
0x0130 | IMG_INFO_COLORSPACE | RW | RO | For lite designs, the expected color space of the incoming video fields. For full designs, the received color space in image information packets. |
0x0134 | IMG_INFO_SUBSAMPLING | RW | RO | For lite designs, the expected chroma subsampling of the incoming video fields. For full designs, the received chroma subsampling in image information packets. |
0x0138 | IMG_INFO_COSITING | RW | RO | For lite designs, the expected chroma co-siting of theincoming video fields. For full designs, the received chroma co-siting in image information packets. |
0x013C | IMG_INFO_FIELD_COUNT | - | RO | The received field count field in image information packets. |
0x0140 | STATUS | RO | Bit 0: status bit. Bit 1: Pending writes bit. |
|
0x0144 | COMMIT | RW | Write 1 to bit 0 to commit the color plane padding values. | |
0x0148 | COLOR_PLANE_0_PAD | RW | Color plane 0 dynamic padding value. | |
0x014C | COLOR_PLANE_1_PAD | RW | Color plane 1 dynamic padding value. | |
0x0150 | COLOR_PLANE_2_PAD | RW | Color plane 2 dynamic padding value. | |
0x0154 | COLOR_PLANE_3_PAD | RW | Color plane 3 dynamic padding value. |
Register Bit Descriptions
Name | Bits | Description |
Color plane manager version ID and product ID | 31:0 | This register always returns 0x6AF7_023B
|
Name | Bits | Description |
Register map version | 7:0 | Register map version. |
IP patch revision | 15:8 | - |
IP update revision | 23:16 | Updated when the IP version changes. |
IP major revision | 31:24 | Updated when the IP version changes. |
Name | Bits | Description |
Lite mode parameterization bit | 0 | Returns 1 if you turn on Lite mode. |
Unused | 31:1 | Unused. |
Name | Bits | Description |
Debug features parameterization bit | 0 | Returns 1 if you turn on Debug features. |
Unused | 31:1 | Unused. |
Name | Bits | Description |
Bits per symbol | 31:0 | Read this register for bits per symbol configuration information. |
Name | Bits | Description |
Number of pixels in parallel | 31:0 | Read this register for pixels in parallel configuration information. |
Name | Bits | Description |
Number of input color planes | 31:0 | Read this register for number of input color planes configuration information. |
Name | Bits | Description |
Number of output color planes | 31:0 | Read this register for number of output color planes configuration information. |
Name | Bits | Description |
Mapping for output color plane 0 | 31:0 | Read this register for the output color plane 0 mapping information.
|
Name | Bits | Description |
Mapping for output color plane 1 | 31:0 | Read this register for the output color plane 1 mapping information.
|
Name | Bits | Description |
Mapping for output color plane 2 | 31:0 | Read this register for the output color plane 2 mapping information.
|
Name | Bits | Description |
Mapping for output color plane 3 | 31:0 | Read this register for the output color plane 3 mapping information.
|
Name | Bits | Description |
Width bits | 15:0 | When you turn on lite mode, write to this register to set the expected width of the incoming video fields. When you turn off lite mode and turn on Debug features, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width. |
unused | 31:16 | Unused. |
Name | Bits | Description |
Height bits | 15:0 | When you turn on lite mode, write to this register to set the expected height of the incoming video fields. When you turn off lite mode and turn on Debug features, this register returns the height-1 field from the most recently received image information packet and adds 1 to return a value for height. |
unused | 31:16 | Unused. |
Name | Bits | Description |
InterlaceNibble bits | 3:0 | When you turn on lite mode, write to this register to set the expected interlacing of the incoming video fields. Whenyou turn off lite mode and turn on Debug features, this register returns the intlaceNibble field from the most recently received image information packet. |
unused | 31:4 | Unused. |
Name | Bits | Description |
CSPcode bits | 6:0 | When you turn on lite mode, write to this register to set the expected color space of the incoming video fields: RGB = 0, YcbCr = 1, YcbCrSD = 2, YcbCrHD = 3, Mono = 4, Raw = 5, RGB565 = 6 When you turn off lite mode and turn on Debug features, this register returns color space information from the most recently received image information packet. |
unused | 31:7 | Unused. |
Name | Bits | Description |
CSPSubSacode bits | 1:0 | When you turn on lite mode, write to this register to set the expected chroma subsampling of the incoming video fields. When you turn off lite mode and turn on Debug features, this register returns the SUBSA field from the most recently received image information packet. |
unused | 31:2 | Unused. |
Name | Bits | Description |
Cositecode bits | 1:0 | When you turn on lite mode, write to this register to set the expected chroma co-siting of the incoming video fields. When you turn off lite mode and turn on Debug features, this register returns the COSITE field from the most recently received image information packet. |
unused | 31:2 | Unused. |
Name | Bits | Description |
Countbits | 6:0 | When you turn on lite mode, this register has no function. When you turn off lite mode and turn on Debug features, this register returns the 7 bit FIELD_COUNT field from the most recently received imageinformation packet. |
unused | 31:7 | Unused. |
Name | Bit | Description |
Status | 0 | The status bit is set if the IP is producing a frame. It returns to 0 in between frames. |
Pending writes | 1 | The pending writes bit is set after a write to:
|
Name | Bit | Description |
Commit | 0 | Write this register to commit new padding values. The values take effect at the start of frame. |
Name | Bits | Description |
Dynamic padding value for output color plane 0 | 31:0 | Write this register to set the output color plane 0 dynamic padding information. If MAPPING_FOR_OUTPUT_COLOR_PLANE0 is not set to 4 (padding), this register has no effect. Write to the COMMIT register for the new padding values to take effect at the next frame. |
Name | Bits | Description |
Dynamic padding value for output color plane 1 | 31:0 | Write this register to set the output color plane 1 dynamic padding information. If MAPPING_FOR_OUTPUT_COLOR_PLANE1 is not set to 4 (padding), this register has no effect. Write to the COMMIT register for the new padding values to take effect at the next frame. |
Name | Bits | Description |
Dynamic padding value for output color plane 2 | 31:0 | Write this register to set the output color plane 2 dynamic padding information. If MAPPING_FOR_OUTPUT_COLOR_PLANE2 is not set to 4 (padding), this register has no effect. Write to the COMMIT register for the new padding values to take effect at the next frame. |
Name | Bits | Description |
Dynamic padding value for output color plane 3 | 31:0 | Write this register to set the output color plane 3 dynamic padding information. If MAPPING_FOR_OUTPUT_COLOR_PLANE3 is not set to 4 (padding), this register has no effect. Write to the COMMIT register for the new padding values to take effect at the next frame. |