Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

29.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)

Locking to an external reference clock involves various bits within the same register. You require multiple writes to control the behavior in the correct sequence and to also ensure that any transition pulses are wide enough.
  1. Always disable the PFD (in case the IP previously uses them):
    1. Disable LPF
      • Write LPF Control 1 Register = 0x0
      • Write LPF Control 3 Register = 0x0
    2. Disable PFD
      • Write PFD Control Register = 0x0
      • Write TxRx VCXO Clock Ratio Register = 0x0
      • Write TxRx Reference Clock Ratio Registers = 0x0
  2. Setup and enable the LPF, which you can do as the PFD is still disabled that feeds the LPF:
    1. Initialize LPF. In this Phase Mode example, the Integrator reset value = 0, P and I gain are 3.0 and 1.0 respectively. D is not used, nor is negative gain or I fraction gain mode. Lock status is Phase mode and shift the LSB position by 1 (for checking lock). Also reset DAC Saturation bit, in case it is set (bit 29, which you need to clear).
      • Write LPF Control 2 Register = 0x0
      • Write LPF Control 1 Register = 0x600d0000
      • Write LPF Control 3 Register = 0x000301
  3. Perform the enable as an extra step (maintain all the other bits, except bit 29, which you should return to ‘0’):
    1. Enable the LPF
      • Read modify write bit 0 LPF control 1 register = 0x400d0001
  4. Setup and enable the PFD by setting the output update period MSBs, the choice of reference clock, its rate, and place the reference clock and VCXO clock in reset in one operation:
    1. Initialize the PFD. In this example, set 10 bits. Set the 10 LSBs to ‘1’ and the upper 6 MSBs to ‘0’. The 16 MSBs multiply the build time value by 1024.
      • Write bits 31:16 PFD Control Register = 0x03ff
    2. In this example choose Ref0 and VCXO clock ratios to be 1:1. They both have theoretically the same frequency value:
      • Write TxRx VCXO clock ratio register = 0x04000000
      • Write TxRx reference clock ratio registers = 0x04000000
    3. Initialize the PFD (reset reference and VCXO clock counters)
      • Write bits 7:4 for the selected clock counter (bit 4 in our example) and bit 12 for VCXO clock counter PFD control register (Reg 0) = 1
  5. Take the internal clock counters out of reset:
    1. Read modify write bits 7:4 for the selected clock counter (bit 4 in the example) and bit 12 for VCXO clock counter PFD control register (Reg 0) = 0.
  6. Enable the PFD:
    Read modify write bit 0 PFD control register (Reg 0) = 0x1
  7. Write the LPF value to drive DAC:
    • Write DAC control register (Reg 5) = 0x3