Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

5. Video and Vision Processing IP Registers

Each IP has an optional memory-mapped control agent interface. When you turn Memory-mapped control interface on in the GUI, the interface connects to your host processor via an Avalon memory-mapped host interface (or via an AXI4 memory-mapped bus through conversion in Platform Designer). It provides a unified method of controlling the IPs.

Every IP has a standard address map when you turn on Memory-mapped control interface. If you turn off Memory-mapped control interface, the IP always processes video data when it is available.

Generally, video and vision processing IP register maps have these distinctive areas:

  • A common area, which contains parameterization information. You can read from IPs to determine their parameters, which allows portability of software and binaries between different video and vision processing platforms.
  • An IP-specific video and vision processing area, which contains functional configuration information for the specific IP.
  • An optional control and debug register area, which allows you to write video field information in lite variants, read video field information in full variants, and to perform other control functions.

Control interfaces use Avalon memory-mapped interfaces. Platform Designer natively supports AXI4-Lite protocols and can automatically adapt to and from Avalon memory-mapped interfaces. Memory interfaces also use Avalon memory-mapped interfaces.

Table 7.  Register Map for Full Variant Video and Vision Processing IPsWith some exceptions (for example coefficient banks) in lite variants, register writes usually take effect at the start of the next field.
Address Register
Parameterization Registers
0x0000 VID_ID
0x0004 VERSION
0x0008 to 0x00FF IP-specific parameterization registers.
0x0100 to 0x011F Reserved for future use.

Reserved for optional Control and debug registers

0x012C Reserved for future use.
IP-specific registers
Read-only registers
0x0140 STATUS
0x0144 to RW_BASE Optional additional read-only registers
Read-write registers
RW_BASE Optional COMMIT register (must be present if any other read-write registers are present)
RW_BASE+4 onwards Optional additional read-write registers

Parameterization registers

The parameterization registers address space occupies from the base address of the IP to a maximum address of 0x011F. The first two registers in this section are the product ID and version registers, so you can identify the IP and the structure of its register map.

The next registers are an optional set of further parameterization information which IPs may populate to inform software on how to control the IP.

For example, a clipper describes clipping using either offsets from the edge of the video or using a top-left corner offset with required height and width. Control software can interrogate the Clipper IP’s parameterization registers to determine which is correct and drive clipping control register accesses accordingly. You can use the same control software across different video pipeline configurations.

The parameterization registers section is followed by an unused area from 0x0100 to 0x011F.

Control and debug registers

You control the IPs in two ways:

  • Provide the input video field information. For example the type of video packets you send to the IP with respect to height, width, or interlacing.
  • Instruct the IP. For example which clipper offsets, mixer offsets, or scaling behavior to apply.

Full variants send image information packets down the video processing pipeline to communicate video field information. Image information packets handle the communication of any resolution changes to downstream IPs. You can control IP functions for full variants via the IP-specific registers.

Communicate video field information and control IP functions for lite variants via the control and IP-specific registers, using the register interface.

Registers 0x0120 to 0x0138 (IMG_INFO_WIDTH to IMG_INFO_COSITING) are the image information registers. For lite variants, write to these to set the dimensions and properties of incoming video fields. For full variants, ignore these registers. However, if you turn on debug features, you can read these registers to retrieve details of the image information fields that the IP receives via the last received image information packet.

Register 0x013C is the IMG_INFO_FIELD_COUNT register. Read this register for full variants when you turn on Debug features for the field count field of the last received image information packet.

Register 0x0140 is the STATUS register. IPs hold the LSB of this register high while they process video packets. The LSB returns low in-between video fields. Bit 1 of this register is the pending register updates bit. The IP sets this bit when you make writes to the IP's register map. The IP automatically clears this bit.

The COMMIT register is at address RW_BASE or later. Write to this register after writing new values to any of the registers in the IP-specific portion of the address map. The IP sets the pending register updates bit of the STATUS register in response and clears it when the new settings take effect.

IP-specific registers

This section of the register map is different for every IP and comprises read and write registers required to control the IP, such as clipping, mixing offsets, color space, or scaling coefficients.

IPs without a memory-mapped control interface

If you turn off Memory-mapped control interface, the IP always processes video data when it is available.