Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

9.3.1. 3D LUT IP Interfaces

The IP has three functional interfaces.
The interfaces are:
  • Intel FPGA video stream input interface
  • Intel FPGA video stream output interface
  • Avalon Memory-Mapped compatible CPU interface

The 3D LUT IP control interface uses Avalon Memory-Mapped protocol to access control and RAM interface registers.


The 3D LUT IP has two clock domains, each with a corresponding reset signal.

Table 43.  Clock domains
Clock name Description
cpu_clock CPU interface clock domain
vid_clock Video processing clock domain

The CPU interface uses little bandwidth and therefore does not impose a minimum clock frequency. The video clock frequency depends on the video resolution, frame rate, and the 3D LUT IP’s number of pixels in parallel. For example, a 300 MHz clock at 2 pixels in parallel supports active video resolutions up to 4096x2160 at 60 Hz.

All RTL-based blocks that transfer or receive data from a different clock domain include clock domain crossing (CDC) circuits for both, single bit and data bus signal cases. The CDC safely allows exchange of data between the two asynchronous clock domains. This principle applies to the control signals from the CPU interface to the main video datapath. The 3D LUT IP includes a .sdc file to constrain this CDC.


Table 44.  Resets associated with clock domainsBoth resets are synchronous active-high
Reset name Description
cpu_reset CPU interface clock domain reset.
vid_reset Video processing clock domain reset.