Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

50.3.1. Block Cache Tool

This tool estimates the minimum suggested size of the warp IP engine’s block cache for the given transform and the number of processing engines. You can use the block cache tool at the design stage to help estimate required FPGA resources and evaluate warps specific to the customer application.

The block cache tool also detects if the configured transform creates a local compression higher than 2:1, which is the maximum supported compression value of the Warp IP. The block cache tool supports both single bounce and double bounce warp IP configurations.

The block cache tool provides a command line interface that allows you to specify the desired warp by using several available options such as rotation, mirroring, keystone, or by using a warp mesh file generated by the Warp SoC Design Example. The tool then estimates block cache usage for all supported block cache sizes. For each size option the tool prints the result in the following form:

Table 1001.  Tool Results
Result Description
Pass Requested warp is possible using this block cache size per processing engine
Pass, Block cache usage too high Requested warp might be possible. However the IP does not guarantee the output quality because of high block cache usage. The configuration requires further evaluation on the target system
Fail Requested warp is not possible using this block cache size. The estimation also fails if the warp exceeds a maximum supported local compression of 2:1, in which case it fails for all block cache sizes

The block cache tool can visualize configured transform by warping a reference image and saving it as a bitmap (bmp) file on the disk.

The block cache tool is delivered with Intel Quartus Prime Software as a Windows command line application at the following location:

<INSTALL_DIR>/ip/altera/vvp/component_library/tcl_cores/intel_vvp_warp/sw/block_cache_tool/windows/bct.exe

where <INSTALL_DIR> is the installation folder of the Intel Quartus Prime software.

Block Cache Tool Options

The block cache tool options:

bct.exe [option]…

Table 1002.  Block Cache Tool Options
Option Description Usage
-h Help

Print the tool usage information.

-iw -ih -ow -oh

Input width (pixels)

Input height (pixels)

Output width (pixels)

Output height (pixels)

Set input and output dimensions of the transformed image in pixels. Default image dimensions are 3840x2160 pixels.
-r

Rotation angle

Set rotation angle in degrees. Image is rotated around the center.
-mh

Mirror horizontally

Mirror image along horizontal axis.

-mv

Mirror vertically

Mirror image along vertical axis.

-ho

Horizontal offset (pixels)

Set horizontal offset in pixels.

-vo

Vertical offset (pixels)

Set vertical offset in pixels.

-hk

Horizontal keystone angle

Set horizontal keystone compensation angle in degrees.

-vk Vertical keystone angle

Set vertical keystone compensation angle in degrees.

-z Zoom

Set image zoom value: less than 1 to zoom out, greater than 1 to zoom in.

-pb

Radial distortion

Set radial distortion compensation value in the range: [-0.45..0.45].

-f

Mesh file name

Path to the warp mesh file generated by the Warp SoC Example application
-e

Number of warp engines.

Number of the warp processing engines. Supported values: 1 or 2 (default);

-db

Double bounce

Assume double bounce Warp IP configuration. By default, the tool assumes Single bounce configuration. Use this option to override default behavior.
-ec

Enable extra compression

Enable compression beyond 2:1. The tool ignores higher than 2:1 local compression if detected.

-s

Run warp simulator

Warp a reference image using provided settings and save result on disk. The output file name is warp_output.bmp.

Examples

This command:

bct.exe -iw 1920 -ih 1080 -ow 3840 -oh 2160 -r 15.0 -s

  • Sets the input resolution to full HD, output resolution to 4K
  • Performs a 15 degree rotation anticlockwise
  • Stores warped reference image on the disk.

The console output is:

intel_vvp_warp block cache tool v1.0
Input resolution: 1920x1080
Output resolution: 3840x2160
Warp engines: 2
Bounce: Single
Generating warp data..
Cache size Result Warnings
256 PASS
512 PASS
1024 PASS  

The console output indicates the IP can perform the configured warp with all available block cache size options.

Figure 131. Warped reference image

This command:

bct.exe -f flying_flag.owf -ec -s

  • Uses the warp mesh file generated by the Warp SoC Example Design, named flying_flag.owf
  • Uses default input and output resolution of 4K
  • Ignores 2:1 local compression limit
  • Stores warped reference image on the disk.

The console output is:

intel_vvp_warp block cache tool v1.0
Input resolution: 3840x2160
Output resolution: 3840x2160
Warp engines: 2
Bounce: Single
Generating warp data...
Cache size Result Warnings
256 PASS Block cache usage too high
512 PASS
1024 PASS

The console output indicates the IP can perform the warp using block cache sizes of 512 and 1024. With the block cache size of 256, the tool detects a high block cache usage. The IP cannot guarantee the output image quality and requires further evaluation on the actual hardware.

Figure 132. Warped reference image

This command:

bct.exe -z 0.45
  • Uses default input and output resolution of 4K
  • Scaled the image down by 0.45

The console output is

intel_vvp_warp block cache tool v1.0
Input resolution: 3840x2160
Output resolution: 3840x2160
Warp engines: 2
Bounce: Single
Generating warp data..
Cache size Result Warnings
256 FAIL
512 FAIL
1024 FAIL

Fails to generate warp data for the given transform using available cache options. Check the transform does not exceed 2:1 compression limit

The console output indicates you have exceeded the maximum compression of 2:1 and therefore the hardware does not support it.