Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

13.4. Black Level Statistics IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 110.  Black Level Statistics Registers

In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_BLS as appropriate and with an optional REG suffix

Address Register Access Description
Lite 20 Full
Parameterization registers
0x0000 VID_PID RO N/A

Read this register to retrieve the ID of the IP.

This register always returns 0x6FA7_0174.

0x0004 VERSION RO N/A Read this register to retrieve the version information for the IP.
0x0008 LITE_MODE RO N/A

Read this register to determine if Lite mode is on.

This register always returns 1.

0x000C DEBUG_ENABLED RO N/A

Read this register to determine if Debug features are on.

This register returns 0 for off and 1 for on.

0x0010 BPS_IN RO N/A Read this register to determine the Bits per color symbol for the input streaming video interface.
0x0014 BPS_OUT RO N/A

Read this register to determine the Bits per color symbol for the output streaming video interface.

The value of this register reads the same for its input counterpart.

0x0018 NUM_COLOR_IN RO N/A Read this register to determine the Number of color planes for the input streaming video interface.
0x001C NUM_COLOR_OUT RO N/A

Read this register to determine the Number of color planes for the output streaming video interface.

The value of this register reads the same for its input counterpart.

0x0020 PIP RO N/A Read this register to determine the Number of pixels in parallel.
0x0024 MAX_WIDTH RO N/A Read this register to determine the Maximum field width.
0x0028 MAX_HEIGHT RO N/A Read this register to determine the Maximum field height.
0x002C to 0x011F - - - Reserved
Control, debug and statistics registers
0x0120 IMG_INFO_WIDTH RW N/A The expected width of the incoming video fields.
0x0124 IMG_INFO_HEIGHT RW N/A The expected height of the incoming video fields.
0x0128 to 0x013F - - - Reserved
0x0140 STATUS RO N/A

Read this register for information about the IP status.

0x0144 FRAME_STATS RO N/A

Read this register for some frame statistics.

0x0148 CFA_00_SUM RO N/A Sum of pixel values in the optical black region for color channel 0.
0x014c CFA_01_SUM RO N/A Sum of pixel values in the optical black region for color channel 1.
0x0150 CFA_10_SUM RO N/A Sum of pixel values in the optical black region for color channel 2.
0x0154 CFA_11_SUM RO N/A Sum of pixel values in the optical black region for color channel 3.

0x0158

COMMIT RW N/A

Write any value to this register to submit changes to the control and region of interest registers.

A pending commit request does not block Freeze Statistics Request of the CONTROL register, which the IP samples continuously.

0x015 c CONTROL RW N/A

Control bits and fields of Black Level Statistics IP

0x0160 H_START RW N/A Region of interest horizontal start value.
0x0164 V_START RW N/A Region of interest vertical start value.
0x0168 H_END RW N/A Region of interest horizontal end value.
0x016c V_END RW N/A Region of interest vertical end value.

Register Bit Descriptions

Table 111.   STATUS
Name Bits Description
Reserved 31:3 Reserved.
Stats are Frozen 2 The IP sets this bit to indicate it stopped updating the statistics.
Commit 1 Pending commit
Running 0 When 1, the IP is processing data.
Table 112.   FRAME_STATS
Name Bits Description
Reserved 31:8 Reserved.
Checksum 7:0 A simple checksum of the frame.
Table 113.   CONTROL
Name Bits Description
Freeze Statistics Request 31 Set this bit to 1 for the IP to start sampling a new set of black level and frame statistics. The IP lowers the Stats are Frozen bit of the STATUS register as a response, and you need to poll Stats are Frozen bit until it is 1 before reading the statistics. The IP expects you to keep Freeze Statistics Request 1 until it raises Stats are Frozen. Set Freeze Statistics Request to 0 before starting over with a new sampling request. Deviating from this flow might result in unexpected IP behavior.
Reserved 30:3 Reserved. Write 0.
Color filter array phase 2:1 Specifies 2x2 color filter order starting from the top left corner of the image.
 00   01   10   11
C0C1 C1C0 C2C3 C3C2
C2C3 C3C2 C0C1 C1C0
Reserved. 0 Reserved. Write 0
Table 114.   H_START
Name Bits Description
Reserved 31:16 Reserved, Write 0.
Position 15:0 Horizontal position of the first pixel in the region of interest. The IP starts counting the pixels from index 0.
Table 115.   V_START
Name Bits Description
Reserved 31:16 Reserved, Write 0
Position 15:0 Vertical position of the first line in the region of interest decremented by 1. The IP starts counts the lines from index 0. Set the value of this register to the real starting line index minus 1. The line counter wraps around. Write 65535 to set vertical starting position to line 0.
Table 116.   H_END
Name Bits Description
Reserved 31:16 Reserved. Write 0.
Position 15:0 Horizontal position of the last pixel in the region of interest incremented by 1. Set this register to point to the first pixel index following the end of the optical black region.
Table 117.   V_END
Name Bits Description
Reserved 31:16 Reserved, write 0.
Position 15:0 Vertical position of the last line in the region of interest. Set this register to point to the last line index of the optical black region.
20 Registers are RW only if you also turn on Debug features, otherwise they are WO.