Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

31.5. Genlock Signal Router IP Software API

intel_vvp_genlock_router_init

prototype:
 int intel_vvp_genlock_router_init(intel_vvp_genlock_router_instance* instance, intel_vvp_core_base base);description:
Description:

Initialization function for a VVP Genlock Router instance.

Attempts to initialize the fields of the Genlock Router and its base core

argument:

instance, pointer to the intel_vvp_ genlock_router _instance to initialize

base, the accessor for the core (on Nios this is a pointer to the base address of the core)

return value:

kIntelVvpCoreOk success

kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID.

kIntelVvpCorePidErr if the product id of the core is not the genlock_router product id

kIntelVvpCoreInstanceErr if the instance parameter is zero (null pointer)

intel_vvp_genlock_router_get_param_vid_pid

prototype:
int intel_vvp_ genlock_router_get_param_vid_pid(intel_vvp_genlock_router_instance* instance);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

return value:

The product ID number

intel_vvp_genlock_router_get_param_version_number

prototype:
int intel_vvp_ genlock_router_get_param_version_number(intel_vvp_genlock_router_instance* instance);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

return value:

The IP version number

intel_vvp_genlock_router_get_param_pulse_length

prototype:
int intel_vvp_ genlock_router_get_param_pulse_length(intel_vvp_genlock_router_instance* instance);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

return value:

The number of clock cycles the start of frame output pulse remains active-high

intel_vvp_genlock_router_get_param_number_of_genlock_inputs

prototype:
int intel_vvp_genlock_router_get_param_number_of_genlock_inputs(intel_vvp_genlock_router_instance*instance);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

return value:

The number of input ports that were selected during build time configuration

intel_vvp_genlock_router_get_param_number_of_genlock_outputs

prototype:
int intel_vvp_genlock_router_get_param_number_of_genlock_outputs(intel_vvp_genlock_router_instance*instance);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

return value:

The number of output ports that were selected during build time configuration

intel_vvp_genlock_router_get_param_genlock_output_type

prototype:
int intel_vvp_genlock_router_get_param_genlock_output_type(intel_vvp_genlock_router_instance*instance);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

return value:

The type of output interface that was selected during build time configuration

intel_vvp_genlock_router_get_param_genlock_input_type

prototype:
int intel_vvp_genlock_router_get_param_genlock_input_type(intel_vvp_genlock_router_instance*instance , uint16_t in_val);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

in_val, the index of the input port

return value:

The type of input interface that was selected during build time configuration for a particular input port

intel_vvp_genlock_router_get_gpio_input

prototype:
int intel_vvp_genlock_router_get_gpio_input(intel_vvp_genlock_router_instance* instance);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

return value:

The data on the general-purpose input register

intel_vvp_genlock_router_get_gpio_output

prototype:
int intel_vvp_genlock_router_get_gpio_output(intel_vvp_genlock_router_instance* instance);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

return value:

The data on the general-purpose output register

intel_vvp_genlock_router_set_gpio_output

prototype:
int intel_vvp_genlock_router_set_gpio_output(intel_vvp_genlock_router_instance* instance, uint32_t out_val);
argument:

instance, pointer to the intel_vvp_genlock_router _instance

out_val, the value that is stored in the general-purpose output register.

return value:

if successful kIntelVvpGenlockRouterOk, otherwise kIntelVvpGenlockRouterInstanceErr

intel_vvp_genlock_router_enable_output_intf

prototype:
int intel_vvp_genlock_router_enable_output_intf(intel_vvp_genlock_router_instance* instance, uint16_t out_port);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

out_port, the index value associated with the output port.

return value:

if successful kIntelVvpGenlockRouterOk, otherwise kIntelVvpGenlockRouterInstanceErr

intel_vvp_genlock_router_disable_output_intf

prototype:
int intel_vvp_genlock_router_disable_output_intf(intel_vvp_genlock_router_instance* instance, uint16_t out_port);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

out_port, the index value associated with the output port.

return value:

if successful kIntelVvpGenlockRouterOk, otherwise kIntelVvpGenlockRouterInstanceErr

intel_vvp_genlock_router_sel_inout_pair

prototype:
intel_vvp_genlock_router_sel_inout_pair(intel_vvp_genlock_router_instance* instance, uint16_t in_port, uint16_t out_port);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

in_port, the index value associated with the input port.

out_port, the index value associated with the output port.

return value:

if successful kIntelVvpGenlockRouterOk, otherwise kIntelVvpGenlockRouterInstanceErr

intel_vvp_genlock_router_get_out_cfg

prototype:
int intel_vvp_genlock_router_get_out_cfg (intel_vvp_genlock_router_instance* instance, uint16_t out_port);
argument:

instance, pointer to the intel_vvp_genlock_router_instance

out_port, the index value associated with the output port.

return value:

The configuration value stored on a particular output register