Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

38.3.1. Stream Cleaner IP Interfaces

Table 683.  Stream Cleaner IP Interfaces
Name Direction Width Description
Clocks and resets
main_clock_clk Input 1 AXI4-S processing clock.
main_reset_rst Input 1 AXI4-S processing reset.
Intel FPGA streaming video interfaces
axi4s_vid_in_tdata Input 104 AXI4-S data in.
axi4s_vid_in_tvalid Input 1 AXI4-S data valid.
axi4s_vid_in_tuser[0] Input 1 AXI4-S start of video frame.
axi4s_vid_in_tuser[1] Input 1 AXI4-S control or data packet.
axi4s_vid_in_tuser[N-1:2] Input 105 Unused.
axi4s_vid_in_tlast Input 1 AXI4-S end of packet.
axi4s_vid_in_tready Output 1 AXI4-S data ready.
axi4s_vid_out_tdata Output 104 AXI4-S data in.
axi4s_vid_out_tvalid Output 1 AXI4-S data valid.
axi4s_vid_out_tuser[0] Output 1 AXI4-S start of video frame.
axi4s_vid_out_tuser[1] Output 1 AXI4-S control or data packet.
axi4s_vid_out_tuser[N-1:2] Output 105 Unused.
axi4s_vid_out_tlast Output 1 AXI4-S end of packet.
axi4s_vid_out_tready Input 1 AXI4-S data ready

The equation gives all tdata widths sizes in these interfaces:

max(2, ceil ((bits per color sample × number of color planes)/8)) × pixels in parallel × 8


This equation gives all tuser widths sizes in these interfaces: N = ceil (tdata width/ 8)