Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

22.3. Defective Pixel Correction IP Functional Description

The Defective Pixel Correction IP identifies defective pixels on 2x2 Bayer images and replaces them with the corrected pixel values.

The IP works on a 5x5 pixel neighborhood.

Figure 58. A Bayer Color Filter ArrayFor an 6x6 section of an image and example pixel neighborhood for green, red, and blue pixels.
Figure 59. Defective Pixel Correction IP Block Diagram

The color channel intensity sorter selects pixels closest to the center pixel and sorts them in order of their intensities. A filter calculates a corrected pixel value from the sorted group of pixels depending on the sensitivity level that you set.

The IP identifies and filters defect pixels dynamically and does not support static defect pixel correction. The sensitivity level determines the filtering strength. When you set the sensitivity level to the weakest value, the IP alters the pixel value only if its original value falls outside the value range of its 5x5 neighborhood. As the sensitivity increases, the range reduces closer to the median value. The IP passes the image unmodified if you set the Bypass bit in the CONTROL register.

You must set the color filter array phase to its correct value, which depends on the framing, rotation, and flipping options you apply to the original image that an imaging sensor captures. If you do not set the correct color filter array phase, the IP may mix color channels and produce incorrect outputs.

Information registers indicate how many pixels the IP modifies on any given frame by the IP. This information can indicate if the sensitivity setting is too high or whether the number of defective pixels is stable, or fluctuates depending on the conditions. These registers provide information about how many pixels are lower (PIX_LO_COUNTER) than the specified sensitivity setting or higher (PIX_HI_COUNTER) (refer to Defective Pixel Correction IP Registers). The IP instantiates these pair of registers for each Number of pixels in parallel. The IP shows the counter values of the instance that you select via PIP Clip Counter Selection value in the CONTROL register. You start updating the counter values by setting the Freeze Stats Request value in the CONTROL register. The IP counts the number of pixels it filters for exactly one frame. The IP sets Stats are Frozen bit of the STATUS register to indicate you may read the counter values. You should clear a previous freeze request and select the counter pair you want the IP to capture before starting a new freeze request.