Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

12.3. Black Level Correction IP Functional Description

The Black Level Correction IP removes the pedestal offset value from the input video stream and resizes the result back to the full dynamic range of the video stream. You write pedestal and scaler values for each of the 4 color channels of the 2x2 color filter array over the external processor interface. The IP uses these values to calculate the output video stream. The IP supports arbitrary 2x2 color filter arrays.
Figure 21. Black Level Correction IP Block Diagram

The pedestal remover subtracts the offset values from the input pixel values. The IP clips negative values to zero if you turn off Reflect around zero, or if you turn on Reflect around zero but set the run-time CONTROL register Clip Zero En bit to turn on clipping to zero. The IP reflects the negative values around zero if you turn on Reflect around zero and clear the run-time CONTROL register Clip Zero En bit to turn off clipping at zero.

Figure 22. The effect of reflection around zero

The scaler part of the IP multiplies the intermediate result after subtraction with an arbitrary factor that you program over the external processor interface. You must calculate the correct multiplication factor from the dynamic range of the video stream and the pedestal value. The IP clips the overflowed values to the maximum value of the output video stream.

You must set the color filter array phase to its correct value, which depends on the framing, rotation, and flipping options you apply on the original image that an imaging sensor captures. If you do not set the correct color filter array phase, the IP may mix color channels and produce incorrect outputs.

Figure 23. Examples of 2x2 Color Filter Arrays For a 6x6 section of an image