Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

28.3. Full-Raster to Streaming Converter Block Description

The IP accepts full-raster video input format as a full-raster interface of pixel data and timing markers embedded in the TDATA bus of an AXI4-S interface. Also, the IP filters out the timing markers from the TDATA bus and provides a video-active only data format on the output interfaces that conforms to the Intel FPGA streaming video protocol specification.
Figure 78. Full-Raster to Streaming Converter high-level block diagram.The figure shows the IP consists of two blocks: a full-raster stripper and an asynchronous FIFO buffer.

The full-raster stripper strips the full-raster timing information from the AXI4-S full-raster stream, leaving active-video data on the AXI4-S lite bus. The IP strips the timing information by setting the AXI4-S TVALID signal low during the blanking interval. When the input AXI4-S full-raster bus sets its TUSER signal high, the IP is in blanking. The stripper holds the TUSER high until the IP transmits the first active pixel.

Figure 79. Full-Raster to Streaming Converter Timing DiagramAn example of how the output TUSER signal is generated by detecting and holding the input TUSER signal on the full-raster video domain, until the first active pixel is detected on the TDATA bus.

The full-raster stripper has a pixel formatter logic, which is mainly based on a barrel shifter logic. It allows the IP to detect the correct position of the start of field for a pixel in parallel scenarios. It aligns the tdata packet content on the output video stream to ensure that the start of field always coincides with pixel 0.

The IP assumes that the transmitter side generates video data with a slower or faster pixel clock rate compared to the receiver video interface. Consequently, moving video data between two different clock domains requires clock domain crossings. Additionally, the TVALID and TREADY flow-controlled AXI4-S video interface may cause the following control-flow problems on the video datapath:

  • Clock-skew matching, if video receiver and transmitter and video processing clocks do not match.
  • In-rush of data if one of the modules in the video pipeline cannot offer the necessary throughput to move the data at the expected rate.

This IP includes an asynchronous output FIFO buffer that handles clock crossing domains between the full-raster and video processing clock domains. Additionally, it temporally accepts data to accommodate a small amount of data-skew mismatching or in-rush data when transferring data between full-raster and active-video only video interfaces.