Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

29.3. Genlock Controller IP Functional Description

The Genlock Controller IP is a feedback control loop system consisting of a phase frequency detector (PFD), a proportional, integral, and derivative (PID) low pass filter (LPF), a pulse width modulation (PWM) digital-to-analog converter (DAC), a profiler module, and a CPU Interface.
Figure 82. Genlock Controller IP Block DiagramThe figure shows the design's submodules

The PFD measures differences between the VCXO input clock (vcxo_clk) and selected reference clock (ref_clk) to produce an error value e(t).

The PID LPF receives the error and accumulates it to produce an output control value c(t) that is proportional to the error. This output control value passes into the PWM DAC that converts it to a series of pulses that drives the external VCXO via a simple external resistor-capacitor (RC) network. The rate of pulses determines a voltage level on the VCXO, which changes the VCXO frequency. Therefore, the PFD output error changes as it is based on the new VCXO clock frequency (hence the feedback). The algorithm continues until the IP minimizes the error value.

The IP aims to reduce the error between the VCXO clock and the reference clock to zero indicating that the clocks must be at the same frequency.

The IP includes a profiler module, which allows measuring receive and transmit pixel clock frequency values. The profiler calculates the latency between receive and transmit SOF toggle pulses. It provides a general purpose output (GPO) bus, which you can map to LEDs to visualize the status of the genlock system.

Generally, the control loop operates in Phase mode or Frequency mode.

In Phase mode, the control loop aims to reduce the delta between the VCXO and selected reference clock measurements to remain in sync. In Frequency mode, the control loop aims to reduce the rate of change between the VCXO and selected reference clock measurements.

The choice of mode depends on requiring hard and soft genlock and the input to output video latencies.

The following factors contribute to the configuration parameters you select for your design:

  • VCXO performance (base frequency, sweep range, reaction time)
  • RC performance
  • Nominal differences between VCXO and reference clocks, including ppm tolerances
  • Rate of tracking required
  • Stability (jitter) of reference clocks
  • Additional error, jitter, and frequency changes that PLLs introduce between the VCXO and FPGA

Tuning the control loop must ensure the loop is stable and lock reasonably quickly. You should test your design using CPU programmable features (such as PID gains) to find the best solution.

PID Controller

The PID controller uses three control terms (proportional, integral, and derivative) to achieve an optimal response to a measured input. The IP reads the difference between the reference and VCXO clock frequencies. It generates a corrective output to modulate the VCXO frequency to match that of the reference clock.

The PID controller continuously calculates an error value e(t) as the difference between two free running counters where one runs off the reference clock and the other the VCXO clock. Calculate an output from e(t) using a control function u(t) to minimise e(t) over time. The control function uses PID terms and is:
Equation 1. Control Function
  • Kp is proportional term which includes a gain factor K. Changes in e(t) cause the proportional effort to react accordingly. No error equates to no proportional effort.
  • Ki denotes the integral term that also includes a gain factor K. The IP integrates e(t) values (post gain) over time. They represent the past historic values of the control effort. The integral stops growing when you eliminate e(t).
  • Kd is the derivative term that can estimate the future trend based on the current rate of change in e(t). Again, it includes a gain factor K.

You must tune the gain values to balance the terms to produce the required step response to the error input. The step response needs to be accurate but also respond timely to achieve lock.

For the genlock controller IP, e(t) is:

e(t) = reference clock counter – vcxo clock counter

It can be positive or negative depending on which clock is faster. It uses 2’s complement maths.

Depending on the ppm differences, e(t) should be of a sufficient value to allow the controller to work using a feedback loop. Consequently, the IP samples e(t) periodically instead of continuously. The period depends on many factors like ppm differences, VCXO reaction time, and lock time.

For the proportional gain, high values produce a large change on the output for a given change to e(t). These high values can cause large over and under shoots of the ideal output value and the control loop can become unstable. However, if the gain is too small, the controller can be less responsive and take a long time to achieve lock.

The integral term is the sum of the sampled e(t) (post gain) over time. The IP uses this term to accelerate towards the ideal output value. As with the proportional term, too high gain can cause over and under shoots and too small causes a slow response time.

In this IP, e(t) experiences jitter from both the recovering input clocks and over time because of temperature. Therefore, it never stays at zero and likely drifts or wobbles around. The IP ensures that at this time small changes in e(t) produce small enough changes to the output to ensure accuracy and achieve genlock. But it must not introduce excessive output jitter that may break any standards specifications (such as SDI).