Visible to Intel only — GUID: evf1697539963223
Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. AXI-Stream Broadcaster Intel® FPGA IP
11. Bits per Color Sample Adapter Intel FPGA IP
12. Black Level Correction Intel® FPGA IP
13. Black Level Statistics Intel® FPGA IP
14. Chroma Key Intel® FPGA IP
15. Chroma Resampler Intel® FPGA IP
16. Clipper Intel® FPGA IP
17. Clocked Video Input Intel® FPGA IP
18. Clocked Video to Full-Raster Converter Intel® FPGA IP
19. Clocked Video Output Intel® FPGA IP
20. Color Plane Manager Intel® FPGA IP
21. Color Space Converter Intel® FPGA IP
22. Defective Pixel Correction Intel® FPGA IP
23. Deinterlacer Intel® FPGA IP
24. Demosaic Intel® FPGA IP
25. FIR Filter Intel® FPGA IP
26. Frame Cleaner Intel® FPGA IP
27. Full-Raster to Clocked Video Converter Intel® FPGA IP
28. Full-Raster to Streaming Converter Intel® FPGA IP
29. Genlock Controller Intel® FPGA IP
30. Generic Crosspoint Intel® FPGA IP
31. Genlock Signal Router Intel® FPGA IP
32. Guard Bands Intel® FPGA IP
33. Histogram Statistics Intel® FPGA IP
34. Interlacer Intel® FPGA IP
35. Mixer Intel® FPGA IP
36. Pixels in Parallel Converter Intel® FPGA IP
37. Scaler Intel® FPGA IP
38. Stream Cleaner Intel® FPGA IP
39. Switch Intel® FPGA IP
40. Tone Mapping Operator Intel® FPGA IP
41. Test Pattern Generator Intel® FPGA IP
42. Unsharp Mask Intel® FPGA IP
43. Video and Vision Monitor Intel FPGA IP
44. Video Frame Buffer Intel® FPGA IP
45. Video Frame Reader Intel FPGA IP
46. Video Frame Writer Intel FPGA IP
47. Video Streaming FIFO Intel® FPGA IP
48. Video Timing Generator Intel® FPGA IP
49. Vignette Correction Intel® FPGA IP
50. Warp Intel® FPGA IP
51. White Balance Correction Intel® FPGA IP
52. White Balance Statistics Intel® FPGA IP
53. Design Security
54. Document Revision History for Video and Vision Processing Suite User Guide
29.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
29.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
29.4.3. Setting the VCXO hold over
29.4.4. Restarting the Genlock Controller IP
29.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
29.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
29.4.7. Disturbing a Reference Clock (a cable pull)
Visible to Intel only — GUID: evf1697539963223
Ixiasoft
8.2. 1D LUT IP Parameters
The IP offers run-time and compile-time parameters.
Parameter | Values | Description |
---|---|---|
Video Data Format | ||
Lite mode | On | The IP only supports lite mode |
Input bits per color sample | 8 to 16 | Select the number of input bits per color sample. |
Output bits per color sample | 8 to 16 | Select the number of output bits per color sample. |
Number of color planes | 1 to 4 | Number of color planes processed per pixel. |
Number of pixels in parallel | 1 to 8 | Select the number of pixels in parallel. |
Maximum Frame Size | ||
Maximum field height | 1k, 2k, 4k, 8k, 16k | Specify the maximum height of incoming frames |
Maximum field width | 2k, 4k, 8k, 16k | Specify the maximum width of incoming frames |
Control Parameters | ||
Equidistant LUT Entries | On or off | Turn on to distribute LUT entries equally across the dynamic range. When off, the IP divides the LUT into segments. When on, the segments at the lower end of the dynamic range are denser. The ones at the upper end are sparser. |
Maximum number of bits to address all LUT entries | 8 to 12 | Maximum number of LUT entries in bits. This value cannot exceed the bits per color sample value. |
Number of bits to address LUT segments | Derived | When Equidistant LUT Entries is on, the IP divides the LUT into segments. The IP derives this parameter from input bits per color sample, maximum number of LUT address bits, and sparsity bit parameters. Only visible when Equidistant LUT Entries is off. |
Sparsity progression across segments (in bits) | 1 to 2 | The sparsity progression factor between neighboring LUT segments in number of address bits. Only available when Equidistant LUT Entries is off. |
Reverse LUT | On or off | Allows you to use the LUT entries in reverse order. |
General | ||
Pipeline ready signal | On or off | Turn on to add extra pipeline registers to the AXI4-S tready signals |
Separate clock for control interface | On or off | Turn on for a separate clock for the control agent interface |
Debug features | On or off | Turn on to read back frame information registers and debugging information registers via the control agent interface. |
Figure 13. 1D LUT IP GUI
![](/content/dam/docs/us/en/683329/24-1/oce1699434637588.png)