1. About This IP Core
2. Getting Started With the 50G Interlaken IP Core
3. 50G Interlaken IP Core Parameter Settings
4. Functional Description
5. 50G Interlaken IP core Signals
6. 50G Interlaken IP Core Register Map
7. 50G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 50G Interlaken IP core
10. 50G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 50G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 40G Ethernet Traffic
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Specifying the 50G Interlaken IP Core Parameters and Options
2.3. Files Generated for Arria V GZ and Stratix V Variations
2.4. Files Generated for Intel® Arria® 10 Variations
2.5. Simulating the 50G Interlaken IP Core
2.6. Integrating Your IP Core in Your Design
2.7. Compiling the Full Design and Programming the FPGA
2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
5.1. 50G Interlaken IP Core Clock Interface Signals
5.2. 50G Interlaken IP Core Reset Interface Signals
5.3. 50G Interlaken IP Core User Data Transfer Interface Signals
5.4. 50G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
5.5. 50G Interlaken IP Core Management Interface
5.6. Device Dependent Signals
5.6.2. Intel® Arria® 10 External PLL Interface Signals
50G Interlaken IP core variations that target an Arria 10 device require an external transceiver PLL to function correctly in hardware. 50G Interlaken IP core variations that target an Arria V or Stratix V device include the transceiver PLLs and do not require that you configure any additional PLLs.
Signal Name |
Direction |
Width (Bits) |
Description |
---|---|---|---|
tx_serial_clk |
Input |
NUM_LANES |
High-speed clock for Intel® Arria® 10 transceiver channel, provided from external TX PLL. |
tx_pll_locked |
Input |
1 |
PLL-locked indication from external TX PLL. |
tx_pll_powerdown | Output |
1 |
Output signal from the IP core internal reset controller. The IP core asserts this signal to tell the external PLLs to power down. |
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