Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents Verify the AFU with ASE

The ASE supports functional verification of AFU RTL code using host application C code developed for the OPAE API without the need for accelerator hardware. The ASE virtualizes the AFU’s physical link with the host, models certain aspects of the OPAE host memory model, and supports communication between the OPAE host application and supported RTL simulation tools used to emulate the AFU running on an actual OPAE-compliant accelerator hardware target.

ASE is useful for verifying your AFU’s interoperability with the rest of the Acceleration Stack using a quick, iterative functional debug environment to minimize time spent in subsequent portions of the AFU development flow that involve more time-intensive steps (for example, PAR, timing closure). ASE also enables a more cost-efficient development environment by removing the dependency on accelerator hardware for early functional debug of AFU interoperability within the Acceleration Stack.

After using the afu_sim_setup to configure a simulation build environment, you are ready to start using ASE to verify your AFU. To know more about the simulations, refer to the Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide and the Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) User Guide