Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents

6.1.1. Instrumenting the AFU Design for Signal Tap

To add Signal Tap instances and debug nodes to your AFU design, follow the procedure outlined in the Generating an AF Build Environment for Source Development section to create a development revision. Once you have created a development revision, use the Signal Tap GUI to instrument the AFU for in-system debug as you normally would. For more information, see the related documentation for Signal Tap.

The nlb_mode_0_stp sample AFU has already been instrumented with Signal Tap and the .stp file is located in the following OPAE SDK directory: $OPAE_PLATFORM_ROOT/hw/samples/nlb_mode_0_stp/hw/par/stp_basic.stp.