Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents Utilizing Clock Resources

The FIM provides several clock resources for use by AFUs. One set of clock resources is the user clock group, which includes uClk_usr and uClk_usrDiv2. Unlike pClk and its derivatives whose frequencies are fixed by the CCI-P Specification, the user clocks can be programmed for a range of frequencies supported by the AFU.

User clocks get provisioned by OPAE when an AF is loaded by the fpgaconf utility. When the fpgaconf utility loads an AF, it configures the PLL in the FIM that sources the user clocks with the frequency specified by a key:value pair found in the AF metadata generated by the packager utility. The desired user clock frequency key:value pair can be specified in a .json file or can be specified with a command line option (overrides entry in the .json file) to the packager utility. You can use the packager to generate AFs with unique metadata user clock frequency values for a single AFU PR bitstream.

The FIM reset resource, pck_cp2af_softReset, is not released until all clock resources are stable and locked, including the user clocks.

The AFU design must close timing on the user clocks at the maximum frequency to be supported by the AFU. Place associated clock timing constraints in a .sdc file and refer to the .sdc file in the AFU's build configuration file.

For usage information on the Packager utility and .json file metadata format, supported keyword parameters, and minimum metadata requirements, refer to the packager tab in the Open Programmable Acceleration Engine (OPAE) Tools User Guide.