Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents

4. The Accelerator Functional Unit (AFU)

The AFU is a function or set of functions that can be accelerated on an OPAE hardware platform. The AFU is described in RTL and then compiled with the OPAE SDK to generate an Accelerated Function (AF) image for the target hardware platform. An AF is a compiled hardware accelerator image implemented in FPGA logic that accelerates an application. The AF image is used by OPAE to load the AFU to the PR region.
An AFU has two main communication paths between the host:
  • FPGA to host transactions: The FPGA accesses host memory (256 terabyte address space) using a 512 bit data path. This data path has separate channels for read and write traffic allowing for simultaneous read and write to occur. The read and write channels support bursts of 1, 2, and 4 cache lines.
  • Host to FPGA (MMIO) transactions: The host can access a 256 KB address space within the FPGA. This address space contains Device Feature Header (DFHs) and the control and status registers of the AFU hardware. DFHs are small ROMs that hold metadata about the hardware that are enumerated by the OPAE SDK.
The AFU can access host memory on a cache line basis (64 bytes) through the CCI-P interface. OPAE defines up to 256 KB of memory mapped I/O (MMIO) space for AFUs that the host can access using the OPAE driver and APIs. At the bottom of the MMIO space, the AFU must implement the following OPAE requirements:
  • AFU DFH - a 64-bit header at MMIO address offset 0x0
  • AFU ID - a 128-bit UUID at MMIO address offset 0x2 (CCI-P D-word address)
The following sections of the CCI-P Reference Manual document the CCI-P protocol and all OPAE requirements for an AFU design, including the DFH and AFU ID format:
  • CCI-P Interface
  • AFU Requirements
  • Device Feature List