Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents

6. AFU In-System Debug

The OPAE SDK provides a remote Signal Tap facility. Use remote Signal Tap to debug an AFU on a target hardware platform. The Signal Tap II Logic Analyzer, included in the Intel® Quartus® Prime Pro Edition, allows you to trigger on AFU signal events and capture traces of signals in your AFU design. The remote capability allows for control of trigger conditions and upload of captured signal traces from a networked workstation running the Signal Tap GUI.

Signal Tap is an in-system logic analyzer that you can use to debug FPGA logic. Conventional (non-remote) Signal Tap uses the physical FPGA JTAG interface and a USB cable to bridge the Intel® Quartus® Prime Signal Tap application running on a host system with the Signal Tap controller instances embedded in the FPGA logic. With Remote Signal Tap, you can achieve the same result without physically connecting to JTAG, which enables signal-level, in-system debug of AFUs deployed in servers where physical access is limited.

In addition to Signal Tap, the remote debug facility in OPAE supports the following in-system debug tools included with the Intel® Quartus® Prime Pro Edition:

  • In-system Sources and Probes
  • In-system Memory Content Editor
  • Signal Probe
  • System Console

This section describes how to generate an AF with remote Signal Tap enabled. This section then describes how to debug a user AFU using OPAE’s mmlink utility, the System Console utility, and Intel® Quartus® Prime Pro Edition.

The nlb_mode_0_stp variation of the nlb_mode_0 sample AFU is used to illustrate how to enable and use remote Signal Tap and can be found in the following location: