Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents The hssi Device Class

The Intel® FPGA PAC platform offers the hssi device class with the raw_pr interface, which consists of a SystemVerilog interface defined in the following Verilog header in the OPAE SDK:

The HSSI interface is used by the AFU to access the network port on the Intel® FPGA PAC platforms. It is composed of the Native PHY Transceiver interface with a generic parallel interface to support multiple configurations by the HSSI PHY in the FIM.

The HSSI interface is an optional interface that AFUs can request from the Intel® FPGA PAC platform. The Intel® FPGA PAC platforms with HSSI interface contain sample AFUs in the directories starting with eth_e2e_e<data_rate> or hssi_prbs