Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card
ID
683129
Date
7/20/2020
Public
1. About this Document
2. Introduction
3. Getting Started with Platform Configuration
4. The Accelerator Functional Unit (AFU)
5. Developing AFUs with the OPAE SDK
6. AFU In-System Debug
7. Accelerator Functional Unit Developer's Guide for Intel® FPGA Programmable Acceleration Card Archives
8. Document Revision History for Accelerator Functional Unit Developer's Guide for Intel® FPGA Programmable Acceleration Card
5.3.2.1. Specify the Platform Configuration
5.3.2.2. Design the AFU
5.3.2.3. AFU Design Guidelines
5.3.2.4. Partial Reconfiguration Design Guidelines
5.3.2.5. Specify the Build Configuration
5.3.2.6. Generate the ASE Build Environment
5.3.2.7. Verify the AFU with ASE
5.3.2.8. Generate the AF Build Environment
5.3.2.9. Generate the AF
5.3.2.1.1. Specify the AFU's UUID
5.3.2.1.2. Request a Top-level Interface
5.3.2.1.3. Extend a Top-level Interface
5.3.2.1.4. Request Device Interface Pipelining
5.3.2.1.5. Request Device Interface Clock-crossing
5.3.2.1.6. Specify a Requested Device as Optional
5.3.2.1.7. Specify AFU User Clock Timing
5.2.2.1. Interface Transforms
The PIM transforms a device class offered by the platform into the specific device interface requested by the AFU. Any device classes on the platform not requested by the AFU are properly terminated to support AF generation. The transformation is typically a simple, direct connection between the platform and AFU consisting of device interface ports or structures or a bundling of the ports into an interface vector. For example, the PIM directly connects the platform’s cci-p interface structures and clocks, power , and error ports to the AFU. In the case of local-memory, the PIM abstracts the hardware platform details from the AFU by packing the platform’s interface into a SystemVerilog interface vector.