Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents

5.2. Overview of the OPAE Platform for AFUs

The PIM defines a generic OPAE Platform for which AFU top-levels should be designed to ensure provisioning on multiple hardware platforms.
The figure below shows how the platform shim generated by the PIM enables AFU integration on a specific target hardware platform.
Figure 3. OPAE Platform Block Diagram

AFUs are designed to use generic top-level interfaces to a set of generic device classes such as a host device (cci-p), local memory, network port I/O, clocks, and power and error management. The AFU requests the device interfaces and properties it needs from the PIM using a platform configuration file specification.