Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

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ID 683129
Date 7/20/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Introduction 3. Getting Started with Platform Configuration 4. The Accelerator Functional Unit (AFU) 5. Developing AFUs with the OPAE SDK 6. AFU In-System Debug 7. Accelerator Functional Unit Developer's Guide for Intel® FPGA Programmable Acceleration Card Archives 8. Document Revision History for Accelerator Functional Unit Developer's Guide for Intel® FPGA Programmable Acceleration Card
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronym List for Accelerator Functional Unit Developer’s Guide 1.4. Acceleration Glossary 1.5. Related Documentation
2. Introduction x
2.1. Getting Started with AFU Development 2.2. Base Knowledge and Skills Prerequisites
2.1. Getting Started with AFU Development x
2.1.1. Development Environment References 2.1.2. FPGA Tools and IP Requirements
4. The Accelerator Functional Unit (AFU) x
4.1. AFU Design Components 4.2. Basic Building Blocks
5. Developing AFUs with the OPAE SDK x
5.1. Overview of the OPAE SDK 5.2. Overview of the OPAE Platform for AFUs 5.3. OPAE SDK Design Flow for AFU Development
5.2. Overview of the OPAE Platform for AFUs x
5.2.1. Platform Device Classes 5.2.2. The Platform Interface Manager (PIM)
5.2.1. Platform Device Classes x
5.2.1.1. The clocks Device Class 5.2.1.2. The cci-p Device Class 5.2.1.3. The power Device Class 5.2.1.4. The error Device Class 5.2.1.5. The hssi Device Class 5.2.1.6. The local-memory Device Class
5.2.2. The Platform Interface Manager (PIM) x
5.2.2.1. Interface Transforms 5.2.2.2. Pipelining 5.2.2.3. Clock Crossing
5.3. OPAE SDK Design Flow for AFU Development x
5.3.1. Overview of the Design Flow 5.3.2. Design Flow Details
5.3.1. Overview of the Design Flow x
5.3.1.1. Minimal Flow Example 5.3.1.2. General Flow Example
5.3.1.1. Minimal Flow Example x
5.3.1.1.1. Specify the Platform Configuration 5.3.1.1.2. Design the AFU 5.3.1.1.3. Specify the Build Configuration 5.3.1.1.4. Generate the AF Build Environment 5.3.1.1.5. Generate the AF
5.3.1.2. General Flow Example x
5.3.1.2.1. Generate the ASE Build Environment 5.3.1.2.2. Verify the AFU with ASE
5.3.2. Design Flow Details x
5.3.2.1. Specify the Platform Configuration 5.3.2.2. Design the AFU 5.3.2.3. AFU Design Guidelines 5.3.2.4. Partial Reconfiguration Design Guidelines 5.3.2.5. Specify the Build Configuration 5.3.2.6. Generate the ASE Build Environment 5.3.2.7. Verify the AFU with ASE 5.3.2.8. Generate the AF Build Environment 5.3.2.9. Generate the AF
5.3.2.1. Specify the Platform Configuration x
5.3.2.1.1. Specify the AFU's UUID 5.3.2.1.2. Request a Top-level Interface 5.3.2.1.3. Extend a Top-level Interface 5.3.2.1.4. Request Device Interface Pipelining 5.3.2.1.5. Request Device Interface Clock-crossing 5.3.2.1.6. Specify a Requested Device as Optional 5.3.2.1.7. Specify AFU User Clock Timing
5.3.2.2. Design the AFU x
5.3.2.2.1. Start with a Top-level Module Template 5.3.2.2.2. Including the Platform Device Interface Definitions 5.3.2.2.3. Using the AFU UUID Header File 5.3.2.2.4. Clock Abstraction for the cci-p Device Interface 5.3.2.2.5. Generating an AF Build Environment for Source Development
5.3.2.3. AFU Design Guidelines x
5.3.2.3.1. General Guidelines 5.3.2.3.2. Utilizing Clock Resources 5.3.2.3.3. Interfacing with the FPGA Interface Manager (FIM)
6. AFU In-System Debug x
6.1. Remote Signal Tap Setup and Use
6.1. Remote Signal Tap Setup and Use x
6.1.1. Instrumenting the AFU Design for Signal Tap 6.1.2. Enable Remote Debug and Signal Tap 6.1.3. Generate the Remote Debug Enabled AF 6.1.4. Prepare the Remote Debug Host 6.1.5. Running a Remote Debug Session 6.1.6. Remote Debug Guidelines 6.1.7. Troubleshooting Remote Debug Connections
6.1.5. Running a Remote Debug Session x
6.1.5.1. Connect to the AFU Target 6.1.5.2. Using Signal Tap with a Remote Target Connection 6.1.5.3. Stimulating the Target AFU for In-System Debug 6.1.5.4. Disconnect from the AFU Target
6.1.5.3. Stimulating the Target AFU for In-System Debug x
6.1.5.3.1. Accessing the AFU in Shared Mode
1. About this Document
2. Introduction
3. Getting Started with Platform Configuration
4. The Accelerator Functional Unit (AFU)
5. Developing AFUs with the OPAE SDK
6. AFU In-System Debug
7. Accelerator Functional Unit Developer's Guide for Intel® FPGA Programmable Acceleration Card Archives
8. Document Revision History for Accelerator Functional Unit Developer's Guide for Intel® FPGA Programmable Acceleration Card

5.3.1.2.2. Verify the AFU with ASE

Type the following commands to compile the AFU and platform simulation models and start the simulation server process: 
cd build_sim

make

make sim

After the commands complete, ASE indicates that the server is ready for simulation. Note the instructions for setting the ASE_WORKDIR environment variable in the ASE client window.

Open a second terminal window and enter the following commands to start the ASE client process: 
<Set ASE_WORKDIR as directed by the simulator in the server window.>

cd $OPAE_PLATFORM_ROOT/hw/samples/hello_afu/sw

make clean

make USE_ASE=1

./hello_afu

The OPAE host application runs on the host in the ASE client window process and the ASE server window process shows the AFU model responding to host MMIO accesses, host memory accesses initiated by the AFU, and interrupt vector information signaled by the AFU.

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