Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents

5.2.2. The Platform Interface Manager (PIM)

The PIM contains a collection of shims. The PlM abstracts the details of the target hardware platform from the AFU to support AFU portability to multiple platforms without modifying the AFU. The PIM performs the following functions based upon the AFU's platform configuration described in its .json file:
  • Validates that an OPAE device interface requested by the AFU is provided by the target platform.
  • Properly terminates any OPAE device class offered by the platform but not requested by the AFU.
  • Enables an AFU to optionally request an OPAE device interface from the target platform and adjust the build-out of its implementation based on whether the requested interface is available. For example, the AFU can optionally request local memory and build-out to use it if available from the target platform, otherwise it builds-out to function without local memory. See the nlb_mode_0 sample AFU for an example.
  • Provides register pipeline stages on requested OPAE device interfaces to aid static timing closure during AF generation.
  • Provides asynchronous clock crossing from an OPAE device interface’s native clock to a target clock requested by the AFU. For example, the AFU can request that all requested OPAE device interfaces be retimed to the uClk_usr clock source provided by the clocks interface. See the hello_mem_afu sample AFU for an example.