Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents Including the Platform Device Interface Definitions

All RTL source in the AFU’s implementation that references device interfaces defined by the OPAE Platform (e.g., cci-p, local-memory) must include the following Verilog header:`include “platform_if.vh”

The top-level AFU RTL module templates in OPAE and the sample AFUs all include platform_if.vh.