Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents

2.2. Base Knowledge and Skills Prerequisites

The Acceleration Stack is a framework and toolset to leverage FPGA technology Most of the platform-level complexity has been abstracted away for the AFU developer by the FPGA Interface Manager (FIM) in the FPGA static region. This guide assumes the following FPGA logic design-related knowledge and skills:

  • Familiarity with PR compilation flows, including the Intel® Quartus® Prime Pro Edition PR flow, concepts of physical and logical partitioning in the FPGA, module boundary best practices, and resource restrictions.

    The hardware compilation flow automates management of the partial reconfiguration region.

  • Knowledge and skills in static timing closure, including familiarity and skill with the Timing Analyzer tool in Intel® Quartus® Prime Pro Edition, applying timing constraints, Synopsys* Design Constraints (.sdc) language and Tcl scripting, and design methods to close timing on critical paths.
  • Knowledge and skills with industry standard RTL simulation tools supported by the Acceleration Stack. For more information, refer to the Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) User Guide.