Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card
ID
683129
Date
7/20/2020
Public
1. About this Document
2. Introduction
3. Getting Started with Platform Configuration
4. The Accelerator Functional Unit (AFU)
5. Developing AFUs with the OPAE SDK
6. AFU In-System Debug
7. Accelerator Functional Unit Developer's Guide for Intel® FPGA Programmable Acceleration Card Archives
8. Document Revision History for Accelerator Functional Unit Developer's Guide for Intel® FPGA Programmable Acceleration Card
5.3.2.1. Specify the Platform Configuration
5.3.2.2. Design the AFU
5.3.2.3. AFU Design Guidelines
5.3.2.4. Partial Reconfiguration Design Guidelines
5.3.2.5. Specify the Build Configuration
5.3.2.6. Generate the ASE Build Environment
5.3.2.7. Verify the AFU with ASE
5.3.2.8. Generate the AF Build Environment
5.3.2.9. Generate the AF
5.3.2.1.1. Specify the AFU's UUID
5.3.2.1.2. Request a Top-level Interface
5.3.2.1.3. Extend a Top-level Interface
5.3.2.1.4. Request Device Interface Pipelining
5.3.2.1.5. Request Device Interface Clock-crossing
5.3.2.1.6. Specify a Requested Device as Optional
5.3.2.1.7. Specify AFU User Clock Timing
5.2.1.6. The local-memory Device Class
The Intel® FPGA PAC platform offers the local-memory device class with the following choice of interfaces:
- avalon_mm - a SystemVerilog interface defined in the following header file in the OPAE SDK:
$OPAE_PLATFORM_ROOT/sw/<opae-version>/platforms/platform_if/rtl/device_if/avalon_mem_if.vh
- avalon_mm_legacy_wires_2bank - a fixed port list of signal wires specific to the Intel® FPGA PAC platform. This interface is for legacy support of AFUs developed with earlier versions of the OPAE SDK. For portability to future platforms, consider porting existing AFUs designed with the legacy interface to the avalon_mm interface.
Note: The new AFU design uses the avalon_mm interface. Intel® recommends to use avalon_mm interface for your new AFU designs and avoid using legacy interface.
The AFU accesses local memory on the Intel® FPGA PAC through the Avalon® Memory-Mapped ( Avalon® -MM) slave interfaces provided by the FIM. The Intel® FPGA PAC platforms typically provide one or more bank of local memory. For detailed information on bank of local memory, refer to the FIM Data Sheet. Each bank interface is synchronous to its own clock source provided by the interface.
The local memory interface is an optional interface that AFUs can request from the Intel® FPGA PAC platform. See the following two sample AFUs for examples of using the local memory interface:
-
$OPAE_PLATFORM_ROOT/hw/samples/hello_mem_afu
-
$OPAE_PLATFORM_ROOT/hw/samples/dma_afu