Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents Interfacing with the FPGA Interface Manager (FIM)

The Intel Acceleration Stack for Intel Xeon CPU with FPGAs Core Cache interface (CCI-P) Reference Manual documents all the requirements for an AFU interfacing with the FIM using the CCI-P protocol. An AFU design must meet all the requirements specified in the following sections of the CCI-P reference manual:
  • CCI-P Interface
  • AFU Requirements
  • Device Feature List

The above sections in the CCI-P reference manual include requirements unique to the Intel Xeon Processor with Integrated FPGA (referred to as Integrated FPGA Platform throughout this document) hardware platform, but most of the information applies to the Intel FPGA PAC. The notable differences between the two platforms are that the Intel® FPGA PACs do not have a UPI channel or second PCIe* link and no accelerator cache is implemented in the FIM.

The hello_afu example AFU included with the Acceleration Stack provides an example implementation of a simple Device Feature List that meets the requirements for an AFU as specified by the CCI-P reference manual. The nlb_mode_0 and dma_afu example AFUs provide example implementations of more featured Device Feature Lists.