Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents

5.3.1. Overview of the Design Flow

This section provides a summary overview of the OPAE SDK design flow for AFU development. Refer to the Design Flow Details for a detailed description of each step included in the flow.

The figure below shows the design flow when using the OPAE SDK to verify and synthesize AFs for a target hardware platform.

The minimal flow depicted in the figure shows the minimum flow steps to generate an AF from an AFU design, while the depiction of the general flow shows where AFU verification with ASE fits in the overall flow.

Figure 4. OPAE SDK Design Flow for AFU Development
  • Specify the Platform Configuration for the AFU in a platform configuration file (.json) by requesting a top-level AFU interface along with any required interface properties. The top-level interface requested by the AFU defines its SystemVerilog top-level module port definition.
  • Design the AFU within this top-level module port definition.
  • With the AFU design file set established, Specify the Build Configuration for both AFU simulation and AF synthesis with a single build configuration file (filelist.txt), which lists the AFU’s design source (e.g., RTL, IP, Platform Designer subsystems, constraints) along with any required macro definitions and include files.
  • Using the PIM, Generate the AF/ASE Build Environment based upon the AFU’s platform and build configuration file specifications and the target hardware platform. At this point in the flow, you can use ASE to run OPAE software applications on a simulation target instantiated from the AFU's RTL source and the hardware platform model provided by OPAE.
  • Finally, Generate the AF using the AF generation scripts provided by the SDK.