Accelerator Functional Unit Developer’s Guide for Intel® FPGA Programmable Acceleration Card

ID 683129
Date 7/20/2020
Document Table of Contents Design the AFU

The AFU’s top-level interface request in its platform configuration file defines its top-level module. The hello_afu sample’s top-level module definition is located here:


The hello_afu sample implements the minimal requirements for an AFU specified in the CCI-P Reference Manual in the AFU submodule instanced by the ccip_std_afu top-level module and is described in the following SystemVerilog source:


The source file includes the afu_json_info.vh Verilog header file generated by the PIM and uses the AFU_ACCEL_UUID macro defined by afu_json_info.vh to set the UUID value as required by the CCI-P Reference Manual.

Each of the above SystemVerilog source files includes the platform_if.vh Verilog header file generated by the PIM, which makes available all the interface definitions used by the AFU.