Intel Accelerator Functional Unit Simulation Environment Quick Start User Guide

ID 683200
Date 3/06/2020
Public

1. About this Document

Updated for:
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.2.1 and 2.0.1

This document describes how to simulate a sample Accelerator Functional Unit (AFU) using the Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) environment. Refer to the Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) User Guide for comprehensive details on ASE capabilities and internal architecture.

The Intel® Accelerator Functional Unit (AFU) Simulation Environment (ASE) is a hardware and software co-simulation environment for any Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC). This software co-simulation environment currently supports the following Intel® FPGA PACs:
  • Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
  • Intel FPGA Programmable Acceleration Card D5005

The ASE provides a transactional model for the Core Cache Interface (CCI-P) protocol and a memory model for the FPGA-attached local memory.

The ASE also validates Accelerator Functional Unit (AFU) compliance to the following protocols and APIs:

  • The CCI-P protocol specification
  • The Avalon® Memory Mapped ( Avalon® -MM) Interface Specification
  • The Open Programmable Acceleration Engine (OPAE)
Table 1.  Acceleration Stack for Intel® Xeon® CPU with FPGAs Glossary
Term Abbreviation Description
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Acceleration Stack

A collection of software, firmware and tools that provides performance-optimized connectivity between an Intel® FPGA and an Intel® Xeon® processor.

Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) Intel® FPGA PAC

PCIe* FPGA accelerator card.

Contains an FPGA Interface Manager (FIM) that pairs with an Intel® Xeon® processor over a PCIe* bus.

Intel® Xeon® Scalable Platform with Integrated FPGA Integrated FPGA Platform

Intel® Xeon® plus FPGA platform with the Intel® Xeon® and an FPGA in a single package and sharing a coherent cache of memory via Ultra Path Interconnect (UPI).