Intel® Agilex™ Device Family Pin Connection Guidelines

ID 683112
Date 9/22/2022
Public
Document Table of Contents

1.9. Notes to Intel® Agilex™ Device Family Pin Connection Guidelines

Note: Intel® recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.

Intel® provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality.

  1. Use the Intel® FPGA Power and Thermal Calculator to determine the preliminary current requirements for VCC and other power supplies. Use the Intel® Quartus® Prime Power Analyzer for the most accurate current requirements for this and other power supplies.
  2. Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.
  3. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express* ( PCIe* ) protocol requires the AC-coupling capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
  4. Low Noise Switching Regulator—defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800 kHz and 1 MHz and has fast transient response. The switching frequency range is not an Intel® requirement.
  5. There are no dedicated PR_REQUEST, PR_ERROR, and PR_DONE pins. If required, you can use user I/O pins for these functions.
  6. The device orientation is die view (bottom of chip view).
  7. All I/O pins in a GPIO bank are configured as tri-stated with weak pull-up enabled during device power up (after VCC is fully powered up) and device configuration. During device power down, the I/O pin signals are measured between GND to VCCIO_PIO voltage level when the VCCIO_PIO and VCC power rails are powering down. All valid data transaction should start after the device enter user mode.
  8. All dedicated configuration/JTAG, SDM, and SDM optional signal pins are in the undetermined state during device power up and power down. All I/O in the SDM pins are configured as defined in the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide during device configuration.
  9. All I/O pins in HPS banks are in the undetermined state during device power up and power down. All I/O in the HPS pins are configured as the Schmitt trigger input with 20-kΩ weak pull-up enabled after the device is powered up and during HPS or device configuration. All HPS data transaction should start after the device is fully powered up.
  10. Input signals of all GPIO, HPS, and SDM I/O pins at any point during power up and power down should not exceed the I/O buffer power supply rail of the bank where the I/O pin resides in. If you use a pin in a GPIO bank with 1.5V VCCIO_PIO, the pin voltage must not exceed the VCCIO_PIO rail or 1.2V, whichever is lower.

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