AN 958: Board Design Guidelines

Download PDF
ID 683073
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Power Distribution Network 2. Gigahertz Channel Design Considerations 3. PCB and Stack-Up Design Considerations 4. Device Pin-Map, Checklists, and Connection Guidelines 5. General Board Design Considerations/Guidelines 6. Memory Interfacing Guidelines 7. Power Dissipation and Thermal Management 8. Tools, Models, and Libraries 9. Reference Designs and Development Kits 10. Document Revision History for AN 958: Board Design Guidelines
1. Power Distribution Network x
1.1. Target Impedance Decoupling Method 1.2. Voltage Regulator Selection 1.3. PDN Design Tool 1.4. Plane Capacitance 1.5. Minimization Parasitic Inductances 1.6. Additional Resources
1.1. Target Impedance Decoupling Method x
1.1.1. FDTIM Decoupling Concepts 1.1.2. Select Decoupling CAPS to Meet ZTARGET
1.1.1. FDTIM Decoupling Concepts x
1.1.1.1. Determining the ZTARGET 1.1.1.2. Determining the fTARGET
1.5. Minimization Parasitic Inductances x
1.5.1. VRM 1.5.2. Decaps 1.5.3. Mounting Inductance 1.5.4. Spreading Inductance 1.5.5. Inter-Plane Capacitance 1.5.6. Conclusion
2. Gigahertz Channel Design Considerations x
2.1. Material Selection and Loss 2.2. Routing Guidelines for Gigabit Channel Designs 2.3. Minimizing Adverse Effects of Material Glass Fiber Weaves 2.4. Plane Cut-outs Below Surface Mount Pads 2.5. Transmitter Pre-Emphasis and Receiver Equalization 2.6. Additional Resources
2.2. Routing Guidelines for Gigabit Channel Designs x
2.2.1. Via Optimization Techniques
2.2.1. Via Optimization Techniques x
2.2.1.1. General Routing Guidelines
3. PCB and Stack-Up Design Considerations x
3.1. Material Selection and Loss 3.2. Board Thickness and Vias 3.3. PCB Recommended Layout Footprint Land Pattern
4. Device Pin-Map, Checklists, and Connection Guidelines x
4.1. High Speed Board Design Advisor 4.2. Complete Pin Connection Table by Device 4.3. Pin Connection Guidelines By Device 4.4. Design for Debug with JTAG Pins 4.5. Hot Socketing, POR and Power Sequencing Support 4.6. Implementing OCT 4.7. Unused I/O Pins Guidelines 4.8. Device Breakout Guidelines 4.9. Additional Resources
5. General Board Design Considerations/Guidelines x
5.1. Board Design Process Overview 5.2. Design Security Features in FPGAs 5.3. EMI 5.4. Discrete Component Selection for High-Speed Design 5.5. S-Parameters 5.6. Smith Chart 5.7. AC Versus DC Coupling 5.8. Additional Resources
5.1. Board Design Process Overview x
5.1.1. Material Selection and Loss 5.1.2. Cross Talk Minimization 5.1.3. Power Filtering/Distribution 5.1.4. Unused I/O Pins 5.1.5. Signal Trace Routing 5.1.6. Ground Bounce 5.1.7. Understanding Transmission Lines 5.1.8. Impedance Calculation 5.1.9. Coplanar Wave Guides 5.1.10. Simultaneous Switching Noise Guidelines
5.1.3. Power Filtering/Distribution x
5.1.3.1. Filtering Noise 5.1.3.2. Distributing Power
5.1.5. Signal Trace Routing x
5.1.5.1. Single Ended Trace Routing 5.1.5.2. Differential Trace Routing 5.1.5.3. Skew Minimization 5.1.5.4. Termination Schemes 5.1.5.5. Termination Design Example 5.1.5.6. Discontinuities Related to a Transmission Path
5.1.5.4. Termination Schemes x
5.1.5.4.1. Simple Parallel Termination 5.1.5.4.2. Thevenin Parallel Termination 5.1.5.4.3. Active Parallel Termination 5.1.5.4.4. Series-RC Parallel Termination 5.1.5.4.5. Series Termination 5.1.5.4.6. Differential Pair Termination 5.1.5.4.7. On-Chip Termination
5.1.5.5. Termination Design Example x
5.1.5.5.1. Determine the Delay 5.1.5.5.2. Determine the Bandwidth 5.1.5.5.3. Using Series Termination 5.1.5.5.4. Using Parallel Termination
5.1.5.6. Discontinuities Related to a Transmission Path x
5.1.5.6.1. Inductive Discontinuity 5.1.5.6.2. Capacitive Discontinuity 5.1.5.6.3. Via Discontinuity 5.1.5.6.4. Right-Angle Bends Related to a Transmission Path
5.1.6. Ground Bounce x
5.1.6.1. Design Guidelines 5.1.6.2. Analyzing Ground Bounce 5.1.6.3. Switching Outputs 5.1.6.4. Quiet Outputs 5.1.6.5. Minimizing Lead Inductance
5.1.8. Impedance Calculation x
5.1.8.1. Microstrip Impedance 5.1.8.2. Stripline Impedance 5.1.8.3. Propagation Delay
5.1.8.3. Propagation Delay x
5.1.8.3.1. Microstrip Layout Propagation Delay 5.1.8.3.2. Stripline Layout Propagation Delay
5.1.9. Coplanar Wave Guides x
5.1.9.1. Simple Coplanar Wave Guide 5.1.9.2. Grounded Coplanar Wave Guide 5.1.9.3. Grounded Differential Coplanar Wave Guide
5.4. Discrete Component Selection for High-Speed Design x
5.4.1. Resistors and Capacitors 5.4.2. Inductors and Ferrite Beads 5.4.3. SMA Connectors
6. Memory Interfacing Guidelines x
6.1. DDR3 Board Design Guidelines 6.2. DDR2 Board Design Guidelines 6.3. DDR Board Design Guidelines 6.4. QDR II and QDR II+ 6.5. RLDRAM II 6.6. Additional Resources
7. Power Dissipation and Thermal Management x
7.1. Power Management Guidelines 7.2. Heat Sinking and Thermal Managment for FPGAs 7.3. Additional Resources
8. Tools, Models, and Libraries x
8.1. Design Tools 8.2. I/O Buffer Models 8.3. Device Libraries 8.4. Net Length Reports 8.5. Thermal Models
9. Reference Designs and Development Kits x
9.1. Development Kits
1. Power Distribution Network
2. Gigahertz Channel Design Considerations
3. PCB and Stack-Up Design Considerations
4. Device Pin-Map, Checklists, and Connection Guidelines
5. General Board Design Considerations/Guidelines
6. Memory Interfacing Guidelines
7. Power Dissipation and Thermal Management
8. Tools, Models, and Libraries
9. Reference Designs and Development Kits
10. Document Revision History for AN 958: Board Design Guidelines

5.1.5.6.3. Via Discontinuity

Avoid vias and layer changes as much as possible when routing a trace because vias slow down edges and cause reflections. Vias are both inductive and capacitive in nature; however, they are dominantly capacitive. A design that uses differential signals requires vias. However, to ensure that the true and complement signals experience the same discontinuity, vias must be in the same configuration for each signal of the differential pair. Thus, any variation in signal due to the via-induced discontinuity is in a common mode. A differential mode discontinuity causes a reduction in the dynamic range.

Blind vias are more expensive, smaller, and act less as a discontinuity than full-sized vias. Blind vias do not go through the PCB and are designed to reduce discontinuity from vias. For better performance when using full-sized vias, use vias in series with the transmission line. The via section that is left hanging behaves like a capacitive stub.

Figure 59 shows an 18-layer board. Layers 1, 3, and 16 are signal layers. Route a trace from layer 1 down to layer 16, rather than routing through layer 3. If you route a trace that stops at layer 3, then the part of the via left hanging behaves like a capacitive stub.

Figure 59. Eighteen-Layer Board with Trace Stub

The capacitive stub effects on a via become more pronounced when the board design involves:

A board thickness of 93 mils, with capacitive stubs, has less impact on a 3.125-Gbps signal as compared to a 200 mils-thick board running at the same frequency. Thus, vias affect signal integrity (at 3.125 Gbps) for boards that are too thick.

When possible, avoid vias and via stubs, and remove any unnecessary pads on vias because the pads create parallel plate capacitance between each other. When designing a 100-mils-thick board, you do not need to back drill the vias for a 3.125-Gbps signal. However, back drilling may be advisable for boards measurably thicker than 100 mils.

A current flow on a transmission line creates a magnetic field. The flux lines induce a return current on the reference structure. When a transmission line has its broadside facing reference planes, most of the return current travels underneath the transmission line at a skin depth on the reference plane. The value of skin depth can be calculated with the following equation:

Where:

You can calculate the current density at any point x in the reference plane with the following equation:

Where:

You should provide a good path for return currents. Figure 60 shows a layer change (from layer 1 to 13) for a pair of differential signals (i.e., red and green structures). The signal starts at point A (in Figure 60) and transmits to point B (Figure 62).

Figure 60, Figure 61, and Figure 62 show that solid reference planes (i.e., light blue structures) are provided for the signal lines.

Create GND islands when necessary. When creating islands of GND, ensure that other signals referencing the plane do not pass over the split. If a signal does pass over the split, its loop increases, also increasing the inductance in the region.

Figure 60. Layer Changes

At the point of the layer change, GND vias should be provided for the return current paths. If the return path does not have GND vias, the return currents look for the closest path, but these paths may not be close enough. In this scenario, the current takes a longer path, increasing its loop. Because of the number of flux lines going through the loop, increasing the loop also increases the inductance. Although Figure 60 only shows two vias, it is better to have more vias circling the signal vias.

Figure 61 is a side view of the layer change view in Figure 60. The signals transmit from layer 1 to the layer 13. Each layer has via pads. Because there is parallel plate capacitance between the pads, the unnecessary pads add capacitive loading. Therefore, remove all of the pads except the ones that directly connect the via to the transmission lines.

Figure 61. Side View of Layer Changes

In Figure 62, a GND island is provided to give a good reference path for the signal. GND vias (i.e., the light blue structures) are brought up to avoid too much discontinuity.

The PCB in Figure 62 does not have enough GND vias, so you should add more around the signal vias, evenly distributed for the two signal lines. In Figure 62, only one side of the differential pair has a GND via close to it.

Figure 62. Transmission Path to Point B

Figure 63 shows a TDR plot that contains an example via from the Stratix® GX development board, a 93-mils thick board. The via looks like a capacitive discontinuity of 0.7 pF. The via connects two transmission lines that are on layer 1 and layer 13 of an 18-layer board.

Figure 63. Capacitive Discontinuity Due to a Via on a 93-mil Thick Board
  • Higher signal speeds
  • Thicker boards
  • Non-essential extra via pads
  • skin depth = 1/√(πƒµoµrσ)
  • ƒ = frequency
  • µo = magnetic permeability of air
  • µr = relative magnetic permeability
  • σ = conductivity of the material
  • Ix = Ioe-x/do
  • Ix = current density at x
  • Io = current density on skin depth
  • x = distance from surface
  • do = skin depth
 
Level Two Title