AN 958: Board Design Guidelines

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ID 683073
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Power Distribution Network 2. Gigahertz Channel Design Considerations 3. PCB and Stack-Up Design Considerations 4. Device Pin-Map, Checklists, and Connection Guidelines 5. General Board Design Considerations/Guidelines 6. Memory Interfacing Guidelines 7. Power Dissipation and Thermal Management 8. Tools, Models, and Libraries 9. Reference Designs and Development Kits 10. Document Revision History for AN 958: Board Design Guidelines
1. Power Distribution Network x
1.1. Target Impedance Decoupling Method 1.2. Voltage Regulator Selection 1.3. PDN Design Tool 1.4. Plane Capacitance 1.5. Minimization Parasitic Inductances 1.6. Additional Resources
1.1. Target Impedance Decoupling Method x
1.1.1. FDTIM Decoupling Concepts 1.1.2. Select Decoupling CAPS to Meet ZTARGET
1.1.1. FDTIM Decoupling Concepts x
1.1.1.1. Determining the ZTARGET 1.1.1.2. Determining the fTARGET
1.5. Minimization Parasitic Inductances x
1.5.1. VRM 1.5.2. Decaps 1.5.3. Mounting Inductance 1.5.4. Spreading Inductance 1.5.5. Inter-Plane Capacitance 1.5.6. Conclusion
2. Gigahertz Channel Design Considerations x
2.1. Material Selection and Loss 2.2. Routing Guidelines for Gigabit Channel Designs 2.3. Minimizing Adverse Effects of Material Glass Fiber Weaves 2.4. Plane Cut-outs Below Surface Mount Pads 2.5. Transmitter Pre-Emphasis and Receiver Equalization 2.6. Additional Resources
2.2. Routing Guidelines for Gigabit Channel Designs x
2.2.1. Via Optimization Techniques
2.2.1. Via Optimization Techniques x
2.2.1.1. General Routing Guidelines
3. PCB and Stack-Up Design Considerations x
3.1. Material Selection and Loss 3.2. Board Thickness and Vias 3.3. PCB Recommended Layout Footprint Land Pattern
4. Device Pin-Map, Checklists, and Connection Guidelines x
4.1. High Speed Board Design Advisor 4.2. Complete Pin Connection Table by Device 4.3. Pin Connection Guidelines By Device 4.4. Design for Debug with JTAG Pins 4.5. Hot Socketing, POR and Power Sequencing Support 4.6. Implementing OCT 4.7. Unused I/O Pins Guidelines 4.8. Device Breakout Guidelines 4.9. Additional Resources
5. General Board Design Considerations/Guidelines x
5.1. Board Design Process Overview 5.2. Design Security Features in FPGAs 5.3. EMI 5.4. Discrete Component Selection for High-Speed Design 5.5. S-Parameters 5.6. Smith Chart 5.7. AC Versus DC Coupling 5.8. Additional Resources
5.1. Board Design Process Overview x
5.1.1. Material Selection and Loss 5.1.2. Cross Talk Minimization 5.1.3. Power Filtering/Distribution 5.1.4. Unused I/O Pins 5.1.5. Signal Trace Routing 5.1.6. Ground Bounce 5.1.7. Understanding Transmission Lines 5.1.8. Impedance Calculation 5.1.9. Coplanar Wave Guides 5.1.10. Simultaneous Switching Noise Guidelines
5.1.3. Power Filtering/Distribution x
5.1.3.1. Filtering Noise 5.1.3.2. Distributing Power
5.1.5. Signal Trace Routing x
5.1.5.1. Single Ended Trace Routing Daisy Chain - With Stub Daisy Chain - Without Stub Star Routing Serpentine Routing 5.1.5.2. Differential Trace Routing 5.1.5.3. Skew Minimization 5.1.5.4. Termination Schemes 5.1.5.5. Termination Design Example 5.1.5.6. Discontinuities Related to a Transmission Path
5.1.5.4. Termination Schemes x
5.1.5.4.1. Simple Parallel Termination 5.1.5.4.2. Thevenin Parallel Termination 5.1.5.4.3. Active Parallel Termination 5.1.5.4.4. Series-RC Parallel Termination 5.1.5.4.5. Series Termination 5.1.5.4.6. Differential Pair Termination 5.1.5.4.7. On-Chip Termination
5.1.5.5. Termination Design Example x
5.1.5.5.1. Determine the Delay 5.1.5.5.2. Determine the Bandwidth 5.1.5.5.3. Using Series Termination 5.1.5.5.4. Using Parallel Termination
5.1.5.6. Discontinuities Related to a Transmission Path x
5.1.5.6.1. Inductive Discontinuity 5.1.5.6.2. Capacitive Discontinuity 5.1.5.6.3. Via Discontinuity 5.1.5.6.4. Right-Angle Bends Related to a Transmission Path
5.1.6. Ground Bounce x
5.1.6.1. Design Guidelines 5.1.6.2. Analyzing Ground Bounce 5.1.6.3. Switching Outputs 5.1.6.4. Quiet Outputs 5.1.6.5. Minimizing Lead Inductance
5.1.8. Impedance Calculation x
5.1.8.1. Microstrip Impedance 5.1.8.2. Stripline Impedance 5.1.8.3. Propagation Delay
5.1.8.3. Propagation Delay x
5.1.8.3.1. Microstrip Layout Propagation Delay 5.1.8.3.2. Stripline Layout Propagation Delay
5.1.9. Coplanar Wave Guides x
5.1.9.1. Simple Coplanar Wave Guide 5.1.9.2. Grounded Coplanar Wave Guide 5.1.9.3. Grounded Differential Coplanar Wave Guide
5.4. Discrete Component Selection for High-Speed Design x
5.4.1. Resistors and Capacitors 5.4.2. Inductors and Ferrite Beads 5.4.3. SMA Connectors
6. Memory Interfacing Guidelines x
6.1. DDR3 Board Design Guidelines 6.2. DDR2 Board Design Guidelines 6.3. DDR Board Design Guidelines 6.4. QDR II and QDR II+ 6.5. RLDRAM II 6.6. Additional Resources
7. Power Dissipation and Thermal Management x
7.1. Power Management Guidelines 7.2. Heat Sinking and Thermal Managment for FPGAs 7.3. Additional Resources
8. Tools, Models, and Libraries x
8.1. Design Tools 8.2. I/O Buffer Models 8.3. Device Libraries 8.4. Net Length Reports 8.5. Thermal Models
9. Reference Designs and Development Kits x
9.1. Development Kits
1. Power Distribution Network
2. Gigahertz Channel Design Considerations
3. PCB and Stack-Up Design Considerations
4. Device Pin-Map, Checklists, and Connection Guidelines
5. General Board Design Considerations/Guidelines
6. Memory Interfacing Guidelines
7. Power Dissipation and Thermal Management
8. Tools, Models, and Libraries
9. Reference Designs and Development Kits
10. Document Revision History for AN 958: Board Design Guidelines

5.1.5.1. Single Ended Trace Routing

A single-ended trace connects the source and the load/receiver. Single-ended traces are used in general point-to-point routing, clock routing, low-speed, and non-critical I/O routing. This section discusses different routing schemes for clock signals. You can use the following types of routing to drive multiple devices with the same clock.

Use the following guidelines to improve the clock transmission line's signal integrity:
  • Daisy chain routing
    • With stub
    • Without stub
  • Star routing
  • Serpentine routing
  • Keep clock traces as straight as possible. Use arc-shaped traces instead of right-angle bends.
  • Do not use multiple signal layers for clock signals.
  • Do not use vias in clock transmission lines. Vias can cause impedance change and reflection.
  • Place a ground plane next to the outer layer to minimize noise. If you use an inner layer to route the clock trace, sandwich the layer between reference planes.
  • Terminate clock signals to minimize reflection.
  • Use point-to-point clock traces as much as possible.

Daisy Chain - With Stub

Daisy chain routing is a common practice in designing PCBs. One disadvantage of daisy chain routing is that stubs, or short traces, are usually necessary to connect devices to the main bus (refer to Figure 18). If a stub is too long, it induces transmission line reflections and degrade signal quality. Therefore, the stub length should not exceed the following conditions:

TDstub < ( T10% to 90% )/3

Where TDstub = Electrical delay of the stubT10% to 90% = Rise or fall time of signal edge

For a 1-ns rise-time edge, the stub length should be less than 0.5 inches. If your design uses multiple devices, all stub lengths should be equal to minimize clock skew. Figure 1 shows stub routing. If possible, you should avoid using stubs in your PCB design. For high-speed designs, even very short stubs can create signal integrity problems.

Figure 18. Daisy Chain Routing with Stubs

Figure 19, Figure 20, and Figure 21 show the SPICE simulation with different stub length. As the stub length decreases, there is less reflection noise, and the eye opening increases due to less reflection noise.

Figure 19. Stub Length = 0.5 Inch
Figure 20. Stub Length = 0.25 Inches
Figure 21. Stub Length = Zero Inches

Daisy Chain - Without Stub

Figure 22 shows daisy chain routing with the main bus running through the device pins, eliminating stubs. This layout removes the risk of impedance mismatch between the main bus and the stubs, minimizing signal integrity problems.

Figure 22. Daisy Chain Routing without Stubs

Star Routing

In star routing, the clock signal travels to all the devices at the same time (refer to Figure 23). Therefore, all trace lengths between the clock source and devices must be matched to minimize the clock skew. Each load should be identical to minimize signal integrity problems. In star routing, you must match the impedance of the main bus with the impedance of the long trace that connects to multiple devices.

Figure 23. Star Routing

Serpentine Routing

When a design requires equal-length traces between the source and multiple loads, you can bend some traces to match trace lengths (refer to Figure 24). Improper trace bends affects signal integrity and propagation delay. To minimize crosstalk, ensure that S ≥ 3 x H, where S is the spacing between the parallel sections and H is the height of the signal trace above the reference ground plane.

Figure 24. Serpentine Routing

It is recommended to avoid serpentine routing if possible. Instead, use arcs to create equal-length traces.

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