220.127.116.11. Single Ended Trace Routing
A single-ended trace connects the source and the load/receiver. Single-ended traces are used in general point-to-point routing, clock routing, low-speed, and non-critical I/O routing. This section discusses different routing schemes for clock signals. You can use the following types of routing to drive multiple devices with the same clock.
- Daisy chain routing
- With stub
- Without stub
- Star routing
- Serpentine routing
- Keep clock traces as straight as possible. Use arc-shaped traces instead of right-angle bends.
- Do not use multiple signal layers for clock signals.
- Do not use vias in clock transmission lines. Vias can cause impedance change and reflection.
- Place a ground plane next to the outer layer to minimize noise. If you use an inner layer to route the clock trace, sandwich the layer between reference planes.
- Terminate clock signals to minimize reflection.
- Use point-to-point clock traces as much as possible.
Daisy Chain - With Stub
Daisy chain routing is a common practice in designing PCBs. One disadvantage of daisy chain routing is that stubs, or short traces, are usually necessary to connect devices to the main bus (refer to Figure 18). If a stub is too long, it induces transmission line reflections and degrade signal quality. Therefore, the stub length should not exceed the following conditions:
TDstub < ( T10% to 90% )/3
Where TDstub = Electrical delay of the stubT10% to 90% = Rise or fall time of signal edge
For a 1-ns rise-time edge, the stub length should be less than 0.5 inches. If your design uses multiple devices, all stub lengths should be equal to minimize clock skew. Figure 1 shows stub routing. If possible, you should avoid using stubs in your PCB design. For high-speed designs, even very short stubs can create signal integrity problems.
Figure 19, Figure 20, and Figure 21 show the SPICE simulation with different stub length. As the stub length decreases, there is less reflection noise, and the eye opening increases due to less reflection noise.
Daisy Chain - Without Stub
Figure 22 shows daisy chain routing with the main bus running through the device pins, eliminating stubs. This layout removes the risk of impedance mismatch between the main bus and the stubs, minimizing signal integrity problems.
In star routing, the clock signal travels to all the devices at the same time (refer to Figure 23). Therefore, all trace lengths between the clock source and devices must be matched to minimize the clock skew. Each load should be identical to minimize signal integrity problems. In star routing, you must match the impedance of the main bus with the impedance of the long trace that connects to multiple devices.
When a design requires equal-length traces between the source and multiple loads, you can bend some traces to match trace lengths (refer to Figure 24). Improper trace bends affects signal integrity and propagation delay. To minimize crosstalk, ensure that S ≥ 3 x H, where S is the spacing between the parallel sections and H is the height of the signal trace above the reference ground plane.
It is recommended to avoid serpentine routing if possible. Instead, use arcs to create equal-length traces.
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