AN 958: Board Design Guidelines

ID 683073
Date 1/28/2022
Public
Document Table of Contents

5.1.6.1. Design Guidelines

It is recommended to follow the below design methods to reduce ground bounce:

Figure 68. Suggested Via Location that Connects to Capacitor Pad
These design guidelines provide information and help for high-speed logic designs operating over a range of PCB conditions.
  • Add decoupling capacitors for as many VCC/GND pairs as possible.
  • Place the decoupling capacitors as close as possible to the power and ground pins of the device.
  • Add external buffers at the output of a counter to minimize the loading on Intel® device pins.
  • Configure the unused I/O pin as an output pin and then drive the output low. This configuration acts as a virtual ground. Connect this low driving output pin to GNDINT and/or the board's ground plane.
  • Any unused I/O pin may be driven to ground by programming the “programmable ground” bit (one per I/O cell). In doing so, the macrocell does not need to be sacrificed, but can be used as a buried macrocell.
  • When speed is not critical, turn on the slow slew rate logic option.
  • Limit load capacitance by buffering loads with an external device, or by reducing the number of devices that drive the bus.
  • Eliminate sockets whenever possible.
  • Reduce the number of outputs that can switch simultaneously and/or distribute them evenly throughout the device.
  • Move switching outputs close to a package ground pin.
  • Create a programmable ground next to switching pins.
  • Eliminate pull-up resistors or use pull-down resistors.
  • Use multi-layer PCBs that provide separate VCC and ground planes.
  • Add appropriate resistors in series to each of the switching outputs to limit the current flow into each of the outputs.
  • Create synchronous designs that are not affected by momentarily switching pins.
  • Assign I/O pins to minimize local bunching of output pins.
  • Place the power and ground pins next to each other. The total inductance is reduced by mutual inductance, because current flows in opposite directions in power and ground pins.
  • Use a bigger via size to connect the capacitor pad to the power and ground plane to minimize the inductance in decoupling capacitors.
  • Use the wide and short trace between the via and the capacitor pad or place the via adjacent to the capacitor pad. Refer to Figure 68.
  • Use surface mount capacitors to minimize the lead inductance.
  • Use low effective series resistance (ESR) capacitors. The ESR should be < 400 mΩ.
  • Each GND pin/via should be connected to the ground plane individually.
  • To add extra capacitance on the board, Intel recommends placing a ground plane next to each power (VCC) plane. This placement gives zero lead inductance and no ESR. The dielectric thickness between the two planes should be ~5 mils.

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