188.8.131.52. Stripline Impedance
A circuit trace routed on the inside layer of the PCB with two low-voltage reference planes (i.e., power and/or GND) constitutes a stripline layout. Use the following equation to calculate the impedance of a stripline trace layout.
Using typical values of W= 9 mil, H= 24 mil, T = 1.4 mil, εr and (FR-4) = 4.1 and solving for stripline impedance (Zo) yields:
Figure 75 shows impedance versus trace width using the stripline trace impedance equation, keeping height and thickness constant for stripline trace.
Figure 76 shows stripline trace impedance versus dielectric height (H) using the stripline trace impedance equation, keeping trace width and trace thickness constant.
As with microstrip layout, the stripline layout impedance also changes inversely proportional to line width and directly proportional to height. However, the rate of change with trace height above GND is much slower in a stripline layout compared to a microstrip layout. A stripline layout has a signal sandwiched by FR-4 material, whereas a microstrip layout has one conductor open to air. This exposure causes a higher, effective dielectric constant stripline layout compared to microstrip layouts. Thus, to achieve the same impedance, the dielectric span must be greater in stripline layouts than in microstrip layouts. Therefore, stripline layout PCBs with controlled impedance lines are thicker than microstrip layout PCBs.
Figure 77 shows stripline trace impedance versus trace thickness using Equation 2, keeping trace width and dielectric height constant. This figure shows that the characteristic impedance decreases as the trace thickness increases.
- Z0 = [(60/√εr) ln (4H/0.67π(T+0.8w))] Ω
- Z0 = [(60/√(4.1)) ln (4(24)/0.67π(1.4)=0.8(9))] Ω
- Z0 ~50 Ω
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