AN 958: Board Design Guidelines

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ID 683073
Date 1/28/2022
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5.1.5.4.3. Active Parallel Termination

Figure 33 shows an active parallel termination scheme, where the terminating resistor (RT = Z0) is tied to a bias voltage (VBIAS). In this scheme, the voltage is selected so that the output drivers can draw current from the high- and low-level signals. However, this scheme requires a separate voltage source that can sink and source currents to match the output transfer rates.

Figure 33. Active Parallel Termination

Figure 34 shows the active parallel fly-by termination scheme.

Figure 34. Active Parallel Fly-By Termination

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