AN 958: Board Design Guidelines

ID 683073
Date 1/28/2022
Document Table of Contents Switching Outputs

When the capacitive loading on the switching outputs increases, the amount of charge available for instantaneous switching increases, which in turn increases the magnitude of ground bounce. Depending on the device, ground bounce increases with capacitive loading until the loading is approximately 100 pF per device output. At this point, the device output buffers reach their maximum current-carrying capacity and inductive factors become dominant.

One method of reducing the capacitive load and, consequently, ground bounce is to connect the device's switching outputs to a bus driver integrated circuit (IC). The outputs of this IC drive the heavy capacitive loads, reducing the loading on the device and minimizing ground bounce for the device's quiet outputs.

Some bus applications use pull-up resistors to create a default high value for the bus. These resistors cause the load capacitances to charge up to the maximum voltage. Consequently, the driving device produces a higher level of ground bounce. Eliminate pull-up resistors in applications in which ground bounce is a concern, or design bus logic that uses pull-down resistors instead.

The number of switching outputs also affects ground bounce. As the number of switching outputs increases, the total charge stored also increases. The total charge is equal to the sum of the stored charges for each switching output. Therefore, the amount of current that must sink to ground increases as the number of switching outputs increases. Ground bounce can increase by as much as 40 to 50 mV for each additional output that is switching.

To counteract these effects, Intel devices provide multiple VCC and GND pin pairs. Reduce ground bounce by moving switching outputs close to a ground pin and distributing simultaneously switching outputs throughout the device.

Besides placing switching pins next to a ground pin, create a programmable ground pin by creating an output pin in the design that drives only ground. By connecting this output pin to ground on the board, the device ground has another connection to the board ground, which helps reduce ground bounce.

Many Intel FPGA devices have slew rate options for the output drivers. Turning on the slow slew rate option for all or most of the drivers slows down the drivers, decreasing di/dt and reducing ground bounce.

To further reduce ground bounce, limit the number of outputs that can switch simultaneously in the design. For functions such as counters, use Gray coding as an alternative to standard sequential binary coding, because only one bit switches at a time.

In extreme cases, adding resistors in series to each of the switching outputs in a high-speed logic device can limit the current flow into each of the outputs and, thus, reduce ground bounce to an acceptable level.


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