AN 958: Board Design Guidelines

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ID 683073
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. Power Distribution Network 2. Gigahertz Channel Design Considerations 3. PCB and Stack-Up Design Considerations 4. Device Pin-Map, Checklists, and Connection Guidelines 5. General Board Design Considerations/Guidelines 6. Memory Interfacing Guidelines 7. Power Dissipation and Thermal Management 8. Tools, Models, and Libraries 9. Reference Designs and Development Kits 10. Document Revision History for AN 958: Board Design Guidelines
1. Power Distribution Network x
1.1. Target Impedance Decoupling Method 1.2. Voltage Regulator Selection 1.3. PDN Design Tool 1.4. Plane Capacitance 1.5. Minimization Parasitic Inductances 1.6. Additional Resources
1.1. Target Impedance Decoupling Method x
1.1.1. FDTIM Decoupling Concepts 1.1.2. Select Decoupling CAPS to Meet ZTARGET
1.1.1. FDTIM Decoupling Concepts x
1.1.1.1. Determining the ZTARGET 1.1.1.2. Determining the fTARGET
1.5. Minimization Parasitic Inductances x
1.5.1. VRM 1.5.2. Decaps 1.5.3. Mounting Inductance 1.5.4. Spreading Inductance 1.5.5. Inter-Plane Capacitance 1.5.6. Conclusion
2. Gigahertz Channel Design Considerations x
2.1. Material Selection and Loss 2.2. Routing Guidelines for Gigabit Channel Designs 2.3. Minimizing Adverse Effects of Material Glass Fiber Weaves 2.4. Plane Cut-outs Below Surface Mount Pads 2.5. Transmitter Pre-Emphasis and Receiver Equalization 2.6. Additional Resources
2.2. Routing Guidelines for Gigabit Channel Designs x
2.2.1. Via Optimization Techniques
2.2.1. Via Optimization Techniques x
2.2.1.1. General Routing Guidelines
3. PCB and Stack-Up Design Considerations x
3.1. Material Selection and Loss 3.2. Board Thickness and Vias 3.3. PCB Recommended Layout Footprint Land Pattern
4. Device Pin-Map, Checklists, and Connection Guidelines x
4.1. High Speed Board Design Advisor 4.2. Complete Pin Connection Table by Device 4.3. Pin Connection Guidelines By Device 4.4. Design for Debug with JTAG Pins 4.5. Hot Socketing, POR and Power Sequencing Support 4.6. Implementing OCT 4.7. Unused I/O Pins Guidelines 4.8. Device Breakout Guidelines 4.9. Additional Resources
5. General Board Design Considerations/Guidelines x
5.1. Board Design Process Overview 5.2. Design Security Features in FPGAs 5.3. EMI 5.4. Discrete Component Selection for High-Speed Design 5.5. S-Parameters 5.6. Smith Chart 5.7. AC Versus DC Coupling 5.8. Additional Resources
5.1. Board Design Process Overview x
5.1.1. Material Selection and Loss 5.1.2. Cross Talk Minimization 5.1.3. Power Filtering/Distribution 5.1.4. Unused I/O Pins 5.1.5. Signal Trace Routing 5.1.6. Ground Bounce 5.1.7. Understanding Transmission Lines 5.1.8. Impedance Calculation 5.1.9. Coplanar Wave Guides 5.1.10. Simultaneous Switching Noise Guidelines
5.1.3. Power Filtering/Distribution x
5.1.3.1. Filtering Noise 5.1.3.2. Distributing Power
5.1.5. Signal Trace Routing x
5.1.5.1. Single Ended Trace Routing 5.1.5.2. Differential Trace Routing 5.1.5.3. Skew Minimization 5.1.5.4. Termination Schemes 5.1.5.5. Termination Design Example 5.1.5.6. Discontinuities Related to a Transmission Path
5.1.5.4. Termination Schemes x
5.1.5.4.1. Simple Parallel Termination 5.1.5.4.2. Thevenin Parallel Termination 5.1.5.4.3. Active Parallel Termination 5.1.5.4.4. Series-RC Parallel Termination 5.1.5.4.5. Series Termination 5.1.5.4.6. Differential Pair Termination 5.1.5.4.7. On-Chip Termination
5.1.5.5. Termination Design Example x
5.1.5.5.1. Determine the Delay 5.1.5.5.2. Determine the Bandwidth 5.1.5.5.3. Using Series Termination 5.1.5.5.4. Using Parallel Termination Time Domain Reflectometry
5.1.5.6. Discontinuities Related to a Transmission Path x
5.1.5.6.1. Inductive Discontinuity 5.1.5.6.2. Capacitive Discontinuity 5.1.5.6.3. Via Discontinuity 5.1.5.6.4. Right-Angle Bends Related to a Transmission Path
5.1.6. Ground Bounce x
5.1.6.1. Design Guidelines 5.1.6.2. Analyzing Ground Bounce 5.1.6.3. Switching Outputs 5.1.6.4. Quiet Outputs 5.1.6.5. Minimizing Lead Inductance
5.1.8. Impedance Calculation x
5.1.8.1. Microstrip Impedance 5.1.8.2. Stripline Impedance 5.1.8.3. Propagation Delay
5.1.8.3. Propagation Delay x
5.1.8.3.1. Microstrip Layout Propagation Delay 5.1.8.3.2. Stripline Layout Propagation Delay
5.1.9. Coplanar Wave Guides x
5.1.9.1. Simple Coplanar Wave Guide 5.1.9.2. Grounded Coplanar Wave Guide 5.1.9.3. Grounded Differential Coplanar Wave Guide
5.4. Discrete Component Selection for High-Speed Design x
5.4.1. Resistors and Capacitors 5.4.2. Inductors and Ferrite Beads 5.4.3. SMA Connectors
6. Memory Interfacing Guidelines x
6.1. DDR3 Board Design Guidelines 6.2. DDR2 Board Design Guidelines 6.3. DDR Board Design Guidelines 6.4. QDR II and QDR II+ 6.5. RLDRAM II 6.6. Additional Resources
7. Power Dissipation and Thermal Management x
7.1. Power Management Guidelines 7.2. Heat Sinking and Thermal Managment for FPGAs 7.3. Additional Resources
8. Tools, Models, and Libraries x
8.1. Design Tools 8.2. I/O Buffer Models 8.3. Device Libraries 8.4. Net Length Reports 8.5. Thermal Models
9. Reference Designs and Development Kits x
9.1. Development Kits
1. Power Distribution Network
2. Gigahertz Channel Design Considerations
3. PCB and Stack-Up Design Considerations
4. Device Pin-Map, Checklists, and Connection Guidelines
5. General Board Design Considerations/Guidelines
6. Memory Interfacing Guidelines
7. Power Dissipation and Thermal Management
8. Tools, Models, and Libraries
9. Reference Designs and Development Kits
10. Document Revision History for AN 958: Board Design Guidelines

5.1.5.5.4. Using Parallel Termination

You can place parallel terminations on either ends or only the far end of the transmission line. You should place terminations as close to the source or destination as possible. Any transmission line between the termination and the end of the transmission line appears as a capacitive load to the signal. If you cannot place terminations close to the integrated circuit (IC), place them after the pin (i.e., fly-by configuration).
  • A 300-ps rise-time signal
  • Two-inch long transmission path between the source and the destination
  • delay = 85√εr ps per inch
  • delay = 85√(0.457εr+0.67) ps per inch
  • V = VFINAL(1–e–t/RC)
  • 0.1 VFINAL = VFINAL (1–e–t1/RC)
  • 0.9 = e–t1/RC
  • 9 = e(t2–t1)/RC
  • ln 9 = (t2–t1)/RC
  • 2.197 = (t2–t1)/RC
  • t2–t1 = Rise time of the signal (Tr) and RC = time constant = r
  • Frequency = 1/2 πr
  • r = RC = 1/2 πf
  • 2.197 = 2 πf Tr
  • f = 0.35/Tr
  • Bandwidth = 0.35/Tr
  • Bandwidth = 0.35/300 ps = 1.16 GHz
  • Speed = Frequency x Wavelength
  • 5.5 giga inches per second = 1.16 GHz x wavelength
  • wavelength = 4.74 in.
  • wavelength/10 = 0.474 in.
  • Reflection coefficient = (ZLOAD – Z0)/(ZLOAD + Z0)

Time Domain Reflectometry

Time domain reflectometry (TDR) is a way to observe discontinuities on a transmission path. The time domain reflectometer sends a pulse through the transmission medium. Reflections occur when the pulse of energy reaches either the end of the transmission path or a discontinuity within the transmission path. From these reflections, the designer can determine the size and location of the discontinuity. This section provides an understanding of TDR.

Figure 45 shows a TDR voltage plot for a cable that is not connected to a PCB. The middle line is a 50-Ω cable one meter long. At point A, a pulse starts (Z0 = 50-Ω) and transmits through the cable, stopping at the end of the transmission line (i.e., Point B). Because the end of the transmission line is open, there is infinite impedance, ZLOAD = α. Therefore, the reflection coefficient at the load is determined with the equation:

The entire signal is reflected. At point B, the amplitude of the signal doubles. Refer to Figure 45.

Figure 45. TDR Voltage Plot with Cable Not Connected to PCB

If the same meter-long cable is then connected to a PCB through an SMA connector, the plot changes. Refer to Figure 46. Because the SMA connector is more capacitive than inductive in nature, it appears as a capacitive load, shown as a dip in the TDR plot.

Figure 46. TDR Voltage Plot with Cable Connected to PCB

Figure 47 shows an expanded curve for the SMA connector. Because the rise time of the pulse sent for TDR analysis is very small (around 20 ps), the TDR voltage plot shows every discontinuity on the transmission path.

The SMA is a capacitive discontinuity on the transmission path, so the signal dips on the voltage plot. The impedance of an ideal transmission line is defined by the following equation:

Therefore, when the capacitance increases, the impedance decreases. If the discontinuity is inductive, then the impedance increases, which appears as a bump in the TDR plot. You can calculate the capacitance and inductance from the curves on a TDR plot. If the plot shows a dip, as in Figure 47, then calculate the capacitance.

Figure 47. TDR Voltage Plot for the Section Around the SMA Connector on PCB

The equivalent circuit approximation for a dip in the TDR plot is a capacitor to ground, as shown in Figure 48.

Figure 48. Equivalent Circuit for a Transmission Line with Capacitive Discontinuity

The RC equation for this type of circuit is:

The two transmission lines behave as if they are parallel to each other.

You can determine the change in voltage (ΔV) and rise time (Tr) from the curve. Then, you can enter the values into the equation (i.e., Z0 = 50 Ω):

Use this equation to determine the RC time constant. You can also use the curve to approximate the RC time constant. Between 0 to 63 percent of the rise is RC. Once the RC is found, you can use it to determine the capacitance (discontinuity, as seen by the signal).

If the discontinuity looks more inductive in nature (i.e., the curve goes up), then the signal experiences a circuit similar to Figure 49. The transmission line is split, with an inductive discontinuity in between.

Figure 49. Equivalent Circuit for a Transmission Line with Inductive Discontinuity

Use the following two equations to find inductive discontinuity (L):

To determine the inductance value, use the equation for (Z0 = 50 Ω):

Figure 50 shows a cross section of a PCB transmission path, which illustrates many discontinuities.

Figure 50. Example TDR Voltage Plot for a Cross Section of a PCB

If you experience a TDR plot similar to Figure 51, calculate the capacitive discontinuity introduced by the SMA connector by factoring in the voltage dip.

Figure 51. TDR Plot for a Section of a PCB

You can determine Tr and V for the equation from the curve as shown in Figure 52.

Figure 52. TDR Plot for the SMA

In this example,

From the equation:

The examples in this section can be used when modeling discontinuity with a simulator. However, instead of using TDR to extract the parasitic for the discontinuity, you can model the discontinuity in the 2D and 3D field solvers.

Reflection coefficient = (ZLOAD – Z0)/(ZLOAD + Z0)

Reflection coefficient in this case = (α– 50)/(α + 50) = 1

Z0 = √(L/C)

R = Z0/2

RC = Z0C/2

(ΔV/250 mV) = 1 - (Tr /2RC)

R = 2Z0

L/R = L/2Z0

(ΔV/250 mV) = 1 - (Tr x Z0 /L)

(ΔV/250 mV) = 1 - (Tr /2RC)

RC = (Tr x 250 mV)/2 (250 mV - ΔV) = 29.9 ps

RC = Z0C/2

If Z0 = 50 Ω, then C = 1.196 pF

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