1. Power Distribution Network
2. Gigahertz Channel Design Considerations
3. PCB and Stack-Up Design Considerations
4. Device Pin-Map, Checklists, and Connection Guidelines
5. General Board Design Considerations/Guidelines
6. Memory Interfacing Guidelines
7. Power Dissipation and Thermal Management
8. Tools, Models, and Libraries
9. Reference Designs and Development Kits
10. Document Revision History for AN 958: Board Design Guidelines
4.1. High Speed Board Design Advisor
4.2. Complete Pin Connection Table by Device
4.3. Pin Connection Guidelines By Device
4.4. Design for Debug with JTAG Pins
4.5. Hot Socketing, POR and Power Sequencing Support
4.6. Implementing OCT
4.7. Unused I/O Pins Guidelines
4.8. Device Breakout Guidelines
4.9. Additional Resources
5.1.1. Material Selection and Loss
5.1.2. Cross Talk Minimization
5.1.3. Power Filtering/Distribution
5.1.4. Unused I/O Pins
5.1.5. Signal Trace Routing
5.1.6. Ground Bounce
5.1.7. Understanding Transmission Lines
5.1.8. Impedance Calculation
5.1.9. Coplanar Wave Guides
5.1.10. Simultaneous Switching Noise Guidelines
5.1.6.5. Minimizing Lead Inductance
Using multi-layer PCBs that provide separate VCC and ground planes can also reduce the ground bounce caused by PCB trace inductance. Wirewrapping the VCC and ground supplies usually increases the amount of ground bounce. To reduce unwanted inductance, use low-inductance bypass capacitors between the VCC supply pins and the board ground plane, as close to the package supply pins as possible. It is required to use low ESR decoupling surface mount capacitors of 0.01 μF to 0.1 μF in parallel to reduce ground bounce. Adding a 0.001 μF capacitor in parallel to these capacitors filters high frequency noise (>100 MHz).
For more information see the Minimizing Ground Bounce & VCC Sag white paper (PDF).