AN 958: Board Design Guidelines

ID 683073
Date 6/26/2023
Document Table of Contents Minimizing Lead Inductance

Using multi-layer PCBs that provide separate VCC and ground planes can also reduce the ground bounce caused by PCB trace inductance. Wirewrapping the VCC and ground supplies usually increases the amount of ground bounce. To reduce unwanted inductance, use low-inductance bypass capacitors between the VCC supply pins and the board ground plane, as close to the package supply pins as possible. It is required to use low ESR decoupling surface mount capacitors of 0.01 μF to 0.1 μF in parallel to reduce ground bounce. Adding a 0.001 μF capacitor in parallel to these capacitors filters high frequency noise (>100 MHz).

For more information see the  Minimizing Ground Bounce & VCC Sag white paper (PDF).