1. Power Distribution Network
2. Gigahertz Channel Design Considerations
3. PCB and Stack-Up Design Considerations
4. Device Pin-Map, Checklists, and Connection Guidelines
5. General Board Design Considerations/Guidelines
6. Memory Interfacing Guidelines
7. Power Dissipation and Thermal Management
8. Tools, Models, and Libraries
9. Reference Designs and Development Kits
10. Document Revision History for AN 958: Board Design Guidelines
4.1. High Speed Board Design Advisor
4.2. Complete Pin Connection Table by Device
4.3. Pin Connection Guidelines By Device
4.4. Design for Debug with JTAG Pins
4.5. Hot Socketing, POR and Power Sequencing Support
4.6. Implementing OCT
4.7. Unused I/O Pins Guidelines
4.8. Device Breakout Guidelines
4.9. Additional Resources
5.1.1. Material Selection and Loss
5.1.2. Cross Talk Minimization
5.1.3. Power Filtering/Distribution
5.1.4. Unused I/O Pins
5.1.5. Signal Trace Routing
5.1.6. Ground Bounce
5.1.7. Understanding Transmission Lines
5.1.8. Impedance Calculation
5.1.9. Coplanar Wave Guides
5.1.10. Simultaneous Switching Noise Guidelines
1.5. Minimization Parasitic Inductances
The goal of a Power Distribution System (PDS) is to provide and maintain a target constant voltage at the power and ground pads of each device. To effectively accomplish this, the PDS relies on the Voltage Regulator Module (VRM), the bulk and decoupling capacitors (Decaps) and the power and ground plane sandwich (plane capacitance). How effectively each of these components perform their job in helping to maintain a constant voltage under varying transient loads depends highly on their associated parasitic inductances.
Section Content
VRM
Decaps
Mounting Inductance
Spreading Inductance
Inter-Plane Capacitance
Conclusion