AN 958: Board Design Guidelines

ID 683073
Date 6/26/2023
Document Table of Contents Differential Pair Termination

Differential signal I/O standards require a termination resistor between the signals at the receiving device (refer to Figure 38). For the LVDS and LVPECL standard, the termination resistor should match the differential load impedance of the bus (i.e., typically 100 Ω). Intel  Stratix® family of devices, and Mercury™ devices have an on-chip termination option. Using on-chip termination decreases required board space.

Figure 38. Differential Pair (LVDS and LVPECL) Termination

Figure 39 shows the differential pair fly-by termination scheme for the LVDS and LVPECL standard.

Figure 39. Pair (LVDS and LVPECL) Fly-By Termination

3.3-V PCML uses two parallel 100-Ω termination resistors at the transmitter and two parallel 50-Ω termination resistors at the receiver (refer to Figure 40). The termination voltage (VT) is the same as the VCCIO voltage (3.3 V).

Figure 40. Differential Pair (3.3 V PCML) Termination

Figure 41 shows the differential pair, fly-by termination scheme for 3.3-V PCML.

Figure 41. Differential Pair (3.3 V PCML) Fly-By Termination