仅对英特尔可见 — GUID: phi1487184675202
Ixiasoft
1.4.3.1. DCLK 和 TCK 信号完整性
The TCK and/or DCLK traces should produce clean signals with no overshoot, undershoot, or ringing. When designing the board, lay out the TCK and DCLK traces with the same techniques used to lay out a clock line. Any overshoot, undershoot, ringing, or other noise on the TCK signal can affect JTAG configuration. A noisy DCLK signal can affect configuration and cause a CRC error. For a chain of devices, noise on any of the TCK or DCLK pins in the chain could cause JTAG programming or configuration to fail for the entire chain.
编号 | 是否完成? | 检查表项目 |
---|---|---|
1 | 将配置DCLK和TCK管脚设计成无噪声的。 |