PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

ID 853726
Date 8/20/2025
Public
Document Table of Contents

4.3. Power Pins

The power pins for Agilex™ 3 VPBGA devices are mainly located in the center BGA area. To ease signal trace routing, there are also some GPIO pins at the edge of the center area.
Figure 18. Power and Ground Pins at the VPBGA Package Center AreaThis figure shows fan-out and routing strategy for Agilex™ 3 VPBGA devices.


The power distribution network (PDN) design guidelines provides the current values and specifications for each power rail. Altera recommends adhering to the following requirements in the PDN guidelines:

  • DC IR drop and PDN transient simulations during the post layout simulation stage are helpful for the design.
  • For a lower inductance connection, keep the power vias connection to the power planes solid and unbroken.