1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs
9.1. Agilex™ 3 Power Distribution Network Design Guidelines Overview
9.2. Power Delivery Overview
9.3. Board Power Delivery Network Recommendations
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
9.5. PCB PDN Design Guideline for Unused GTS Transceiver
9.6. PCB Voltage Regulator Recommendation for PCB Power Rails
9.7. Board PDN Simulations
9.8. Agilex™ 3 Device Family PDN Design Summary
4.3. Power Pins
The power pins for Agilex™ 3 VPBGA devices are mainly located in the center BGA area. To ease signal trace routing, there are also some GPIO pins at the edge of the center area.
Figure 18. Power and Ground Pins at the VPBGA Package Center AreaThis figure shows fan-out and routing strategy for Agilex™ 3 VPBGA devices.
The power distribution network (PDN) design guidelines provides the current values and specifications for each power rail. Altera recommends adhering to the following requirements in the PDN guidelines:
- DC IR drop and PDN transient simulations during the post layout simulation stage are helpful for the design.
- For a lower inductance connection, keep the power vias connection to the power planes solid and unbroken.
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