PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

ID 853726
Date 8/20/2025
Public
Document Table of Contents

3.7. PCB Vias

  • Minimize vias for high-speed differential channels because they can increase channel lost and affect the timing budget.
  • Keep impedance continuity between the high-speed PCB via and trace. Vias typically have higher capacitance and lower impedance than traces.
  • Optimize via impedance using a 3D electromagnetic (EM) field solver by sweeping the anti-pad width, length, and radius for your specific PCB stack-up, drill size, and via stub.
  • Keep in mind that:
    • The smaller the drill size, the higher the via impedance.
    • The larger the anti-pad size, the higher the via impedance.
    • The shorter the via stub, the higher the via impedance.
    • The smaller the via top, bottom, and functional pads, the higher the via impedance.
  • Make sure that each high-speed signal via has an associated ground via for reference.
  • Make sure that the two signal vias of a differential pair have symmetrical ground vias.
  • Remove non-functional pads for high-speed signal vias and ground vias to lower via capacitance.
  • Make the closest transmit and receive signal via coupling length as short as possible through an appropriate layer assignment.