1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs
9.1. Agilex™ 3 Power Distribution Network Design Guidelines Overview
9.2. Power Delivery Overview
9.3. Board Power Delivery Network Recommendations
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
9.5. PCB PDN Design Guideline for Unused GTS Transceiver
9.6. PCB Voltage Regulator Recommendation for PCB Power Rails
9.7. Board PDN Simulations
9.8. Agilex™ 3 Device Family PDN Design Summary
3.7. PCB Vias
- Minimize vias for high-speed differential channels because they can increase channel lost and affect the timing budget.
- Keep impedance continuity between the high-speed PCB via and trace. Vias typically have higher capacitance and lower impedance than traces.
- Optimize via impedance using a 3D electromagnetic (EM) field solver by sweeping the anti-pad width, length, and radius for your specific PCB stack-up, drill size, and via stub.
- Keep in mind that:
- The smaller the drill size, the higher the via impedance.
- The larger the anti-pad size, the higher the via impedance.
- The shorter the via stub, the higher the via impedance.
- The smaller the via top, bottom, and functional pads, the higher the via impedance.
- Make sure that each high-speed signal via has an associated ground via for reference.
- Make sure that the two signal vias of a differential pair have symmetrical ground vias.
- Remove non-functional pads for high-speed signal vias and ground vias to lower via capacitance.
- Make the closest transmit and receive signal via coupling length as short as possible through an appropriate layer assignment.