PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

ID 853726
Date 8/20/2025
Public
Document Table of Contents

6.1. General DDR Signal Routing Guideline on PCB

Altera recommends routing all data signals within a specific group on the same layer. This section provides both stripline and microstrip routing guidelines for all supported EMIF interfaces and topologies.

Route the data group signals (DQ, DM and DQS signals) on shallow layers—stripline or microstrip line. For better performance, use the shortest Z-height via transitions to avoid vertical crosstalk.

Long via stubs affects the channel ISI, however the impact of ISI is less than the impact of crosstalk for the maximum data rate performance.

Figure 28. Case A Routing is Suggested for Data Group Signals Over Case B

To minimize horizontal crosstalk between signals on the same layer, Altera recommends maintaining adequate signal trace–to–trace (edge to edge) space. Keep a minimum spacing of 3× H2 separation distance for inner layer as shown in the following figure. Certain signals within the same group can have smaller spacing, such as DQ to DQ. For more details about the spacing requirement, refer to the respective routing guide sections for each signal group.

Figure 29. Minimum Trace-to-Trace Separation Distance
2 'H' is the dielectric thickness to the closest reference plane.