PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

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ID 853726
Date 8/20/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. BGA Footprint and Land Pattern 3. General PCB Design Considerations 4. VPBGA PCB Routing Guidelines 5. MBGA PCB Routing Guidelines 6. EMIF PCB Routing Guidelines (VPBGA and MBGA) 7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 8. True Differential I/O Interface PCB Routing Guidelines 9. Power Distribution Network Design Guidelines 10. Document Revision History for the PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs
1. Overview x
1.1. Agilex™ 3 FPGAs and SoCs Packages
2. BGA Footprint and Land Pattern x
2.1. Metal-Defined Board Pad 2.2. Spoked Pad 2.3. Wide Trace Metal-Defined Pad 2.4. Solder Mask-Defined Pad 2.5. Recommended Land Patterns
3. General PCB Design Considerations x
3.1. Impedance Tolerances 3.2. Reference Planes 3.3. Layer Assignment 3.4. Via Drill Size 3.5. Fiber Weave 3.6. PCB Traces 3.7. PCB Vias 3.8. AC Coupling Capacitors 3.9. Other Considerations
3.6. PCB Traces x
3.6.1. Zig-Zag Routing 3.6.2. Image Rotation
4. VPBGA PCB Routing Guidelines x
4.1. Pin Distribution and Ball Pitches 4.2. Fan-Out and Routing Strategy 4.3. Power Pins
5. MBGA PCB Routing Guidelines x
5.1. Typical Design Rules For Type-IV HDI in a 0.5 mm MBGA 5.2. HSSI Breakout 5.3. EMIF Breakout 5.4. GTS Transceiver PCIe* 3.0 Interface Design Guidelines 5.5. GTS Transceiver Ethernet 10G NRZ Interface Design Guidelines 5.6. DisplayPort Connectors 5.7. HDMI Connectors
5.4. GTS Transceiver PCIe* 3.0 Interface Design Guidelines x
5.4.1. Channel Recommendations 5.4.2. General Guidelines for PCIe* 3.0 Interface 5.4.3. PCIe* Add-In Card Edge Finger
5.5. GTS Transceiver Ethernet 10G NRZ Interface Design Guidelines x
5.5.1. Channel Recommendations 5.5.2. General Guidelines for Ethernet Interface 5.5.3. Quad Small Form-factor Pluggable and Small Form-factor Pluggable Connector Routing
6. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
6.1. General DDR Signal Routing Guideline on PCB 6.2. General Notes for EMIF Routing Guidelines Table 6.3. LPDDR4 Interface Design Guidelines 6.4. LPDDR4 Simulation Strategy
6.1. General DDR Signal Routing Guideline on PCB x
6.1.1. FPGA DDR Break Out Routing 6.1.2. DRAM Break Out in Layout Routing 6.1.3. Ground Plane and Return Path
6.3. LPDDR4 Interface Design Guidelines x
6.3.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface) 6.3.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
8. True Differential I/O Interface PCB Routing Guidelines x
8.1. True Differential I/O Specifications
9. Power Distribution Network Design Guidelines x
9.1. Agilex™ 3 Power Distribution Network Design Guidelines Overview 9.2. Power Delivery Overview 9.3. Board Power Delivery Network Recommendations 9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 9.5. PCB PDN Design Guideline for Unused GTS Transceiver 9.6. PCB Voltage Regulator Recommendation for PCB Power Rails 9.7. Board PDN Simulations 9.8. Agilex™ 3 Device Family PDN Design Summary
9.2. Power Delivery Overview x
9.2.1. Power Architecture 9.2.2. Rail Merger Requirements 9.2.3. Power Rails Specification 9.2.4. Decoupling Capacitors Recommendation
9.2.1. Power Architecture x
9.2.1.1. Power Budget 9.2.1.2. Power Tree
9.2.3. Power Rails Specification x
9.2.3.1. Power Nets 9.2.3.2. Power Rails Tolerance 9.2.3.3. Power Nets and Transient Specifications
9.2.3.1. Power Nets x
9.2.3.1.1. Agilex™ 3 Package Power Nets and Subsystems Details
9.2.4. Decoupling Capacitors Recommendation x
9.2.4.1. Agilex™ 3 FPGA Packages Board-Level Decoupling Capacitors Summary 9.2.4.2. Agilex™ 3 GTS Transceiver Board-Level Decoupling Capacitors Summary
9.3. Board Power Delivery Network Recommendations x
9.3.1. Board Decoupling Capacitors Guide 9.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 9.3.3. Remote Sense Connections 9.3.4. Load Line Requirements 9.3.5. VCC Core Board Current Slew Rate
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
9.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation Under Noisy Voltage Regulator
9.5. PCB PDN Design Guideline for Unused GTS Transceiver x
9.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

3.6. PCB Traces

  • Use stripline routing for better far end crosstalk performance and a tight impedance tolerance. Keep the trace length shorter than the maximum allowed length, limited by the full-channel insertion loss (IL) and eye diagram simulation results.
  • Consider using microstrip routing in a high-density PCB design with fewer layers. Because the microstrip routing may affect the impedance control tolerance and total insertion loss, Altera recommends that you perform a simulation to verify them, especially when implementing long microstrip length.
  • Follow the general stripline pair-to-pair spacing rules:
    • 5× H1 for transmitter-to-transmitter and receiver-to-receiver
    • 9× H1 for transmitter-to-receiver, transmitter-to-others, and receiver-to-others
  • Use a solid ground reference for high-speed differential pairs.
  • Keep at least 5× H1 of spacing between the edge of a trace and the void, and between the edge of a trace and the edge of the reference plane in the open field area.
  • Maintain symmetrical routing between two signals that comprise a differential pair from end-to-end, including the trace length, the transition vias location, and the placement of AC coupling capacitors. Maintaining this symmetry prevents introducing differential-to-common-mode or common-to-differential-mode conversion AC noise.
    Figure 6. Symmetrical and Non-Symmetrical Routing Examples


  • Breakout routing usually has a smaller trace width and smaller pair-to-pair spacing. Keep the breakout routing as short as possible to minimize the reflection and the insertion loss, and reduce crosstalk.
  • To mitigate near end crosstalk, route the high-speed transmitter and receiver signals on different layers, or separate the TX and RX signals with large spacing of at least 9× H1 in the stripline layer.
  • In the BGA pin field via array, avoid high-speed traces routing between two vias that comprise a differential pair via. Minimize the coupling area between the high-speed trace and via.
  • To increase the common mode noise immunity, start the differential pair P/N deskew at the transmitter and end deskew at the receiver. Compensate for the skew after the skew happens and close to the point where the variation occurs.
    Figure 7. Intrapair Deskew Close to the Skew Location


  • Minimize serpentine layouts, making them transparent to the signal. Serpentine layouts introduce discontinuity to the differential channel. You can minimize the discontinuity by making the electrical length shorter than the signal rise time. In general, keep the serpentine routing length less than 100 mil with 45° arcs and bends. A loosely-coupled differential pair is less affected by serpentine lines.
    Figure 8. Deskew Trombone Routing Rule


  • Use arc routing for high-speed differential traces.
  • Use teardrop traces for high-speed differential traces in the pad and via area.
  • Mitigate the fiber weave effect with techniques like zig-zag routing and image rotation.

Section Content
Zig-Zag Routing
Image Rotation

Related Information
1 'H' is the distance from the signal layer to the closest reference layer
Level Two Title